From: Matthew Wilcox <matthew@wil.cx>
To: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Cc: davem@davemloft.net, netdev@vger.kernel.org, gospo@redhat.com,
Alexander Duyck <alexander.h.duyck@intel.com>,
linux-pci <linux-pci@vger.kernel.org>,
Matthew Wilcox <willy@linux.intel.com>,
Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [net-next PATCH 1/2] PCI: Add PCI quirk to disable L0s ASPM state for 82575 and 82598
Date: Tue, 3 Mar 2009 21:05:26 -0700 [thread overview]
Message-ID: <20090304040526.GB1884@parisc-linux.org> (raw)
In-Reply-To: <20090304020308.15176.40527.stgit@lost.foo-projects.org>
On Tue, Mar 03, 2009 at 06:03:09PM -0800, Jeff Kirsher wrote:
> From: Alexander Duyck <alexander.h.duyck@intel.com>
>
> This patch is intended to disable L0s ASPM link state for 82598 (ixgbe)
> parts due to the fact that it is possible to corrupt TX data when coming
> back out of L0s on some systems. The workaround had been added for 82575
> (igb) previously, but did not use the ASPM api. This quirk uses the ASPM
> api to prevent the ASPM subsystem from re-enabling the L0s state.
>
> Instead of adding the fix in igb to the ixgbe driver as well it was
> decided to move it into a pci quirk. It is necessary to move the fix out
> of the driver and into a pci quirk in order to prevent the issue from
> occuring prior to driver load to handle the possibility of the device being
> passed to a VM via direct assignment.
Thanks for the explanation, it handles my immediate question of "why do
it in a quirk?" It does, however, raise the very interesting question
about what to do about other devices which have issues that are currently
handled in the driver that can't be handled by the driver in a VM.
I don't have a good example to hand right now, but I bet I can spot one
when I'm less tired.
> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
> CC: linux-pci <linux-pci@vger.kernel.org>
> CC: Matthew Wilcox <willy@linux.intel.com>
> CC: Jesse Barnes <jbarnes@virtuousgeek.org>
I'm not going to ack this patch at this point, let's just give it a day.
FWIW, Jesse is not going to be able to review patches this week.
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
next prev parent reply other threads:[~2009-03-04 4:05 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-04 2:03 [net-next PATCH 1/2] PCI: Add PCI quirk to disable L0s ASPM state for 82575 and 82598 Jeff Kirsher
2009-03-04 2:03 ` [net-next PATCH 2/2] igb: remove ASPM L0s workaround Jeff Kirsher
2009-03-04 4:05 ` Matthew Wilcox [this message]
2009-03-06 0:31 ` [net-next PATCH 1/2] PCI: Add PCI quirk to disable L0s ASPM state for 82575 and 82598 David Miller
2009-03-06 1:02 ` Matthew Wilcox
2009-03-06 1:44 ` David Miller
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20090304040526.GB1884@parisc-linux.org \
--to=matthew@wil.cx \
--cc=alexander.h.duyck@intel.com \
--cc=davem@davemloft.net \
--cc=gospo@redhat.com \
--cc=jbarnes@virtuousgeek.org \
--cc=jeffrey.t.kirsher@intel.com \
--cc=linux-pci@vger.kernel.org \
--cc=netdev@vger.kernel.org \
--cc=willy@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.