Re: [PATCH v2] tlv320aic3x: disable ADC/DAC while changing clock

[Mark Brown <broonie@sirena.org.uk>]

On Thu, Apr 02, 2009 at 10:39:12AM +0300, Jarkko Nikula wrote:

> > Hrm, does the chip support asymmetric configurations for playback and
> > capture?

> My two cents: It supports different sampling rates for ADC and DAC but
> I don't believe there is practical use or HW doing this. In this setup
> there is separate word clock signal on GPIO1 for ADC.

Hrm, that's fairly common for hardware - even with shared LRCLK many
devices will be able to support asymmetric rates providing there are
enough BCLKs to drive the data.  Presumably the only limit in the codec
itself is going to be that whatever the PLL is set for will be the
maximum.

Being a bit stricter than is required probaly won't hurt; someone can
always relax things later on if required.

> Unfortunately I'm bit off from the actual issue here but I remember some
> TI codec had requirement to keep DAC/ADC off while changing the
> configuration...

Yes, that's the issue that Daniel is fixing here - it's not possible to
change the clocking (or at least the PLL) while a DAC or ADC is active.