From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LrJ9c-0000J5-6t for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:48:24 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LrJ9b-0000IZ-F6 for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:48:23 -0400 Received: from [199.232.76.173] (port=50055 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LrJ9b-0000IP-6h for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:48:23 -0400 Received: from hall.aurel32.net ([88.191.82.174]:53578) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LrJ9a-0003Lm-Ie for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:48:22 -0400 Date: Tue, 7 Apr 2009 23:48:19 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes. Message-ID: <20090407214819.GF23682@volta.aurel32.net> References: <1238423794-25455-1-git-send-email-gingold@adacore.com> <1238423794-25455-2-git-send-email-gingold@adacore.com> <1238423794-25455-3-git-send-email-gingold@adacore.com> <1238423794-25455-4-git-send-email-gingold@adacore.com> <1238423794-25455-5-git-send-email-gingold@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1238423794-25455-5-git-send-email-gingold@adacore.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tristan Gingold Cc: qemu-devel@nongnu.org On Mon, Mar 30, 2009 at 04:36:19PM +0200, Tristan Gingold wrote: > This is necessary for alpha because it has 4 protection levels and pal mode. > > Signed-off-by: Tristan Gingold Thanks, applied. > --- > exec.c | 30 +++++++++++++++++++++++++----- > softmmu_exec.h | 29 ++++++++++++++++++++++++----- > 2 files changed, 49 insertions(+), 10 deletions(-) > > diff --git a/exec.c b/exec.c > index 5dc6bc7..7c2def0 100644 > --- a/exec.c > +++ b/exec.c > @@ -1736,12 +1736,18 @@ void tlb_flush(CPUState *env, int flush_global) > env->tlb_table[2][i].addr_read = -1; > env->tlb_table[2][i].addr_write = -1; > env->tlb_table[2][i].addr_code = -1; > -#if (NB_MMU_MODES == 4) > +#endif > +#if (NB_MMU_MODES >= 4) > env->tlb_table[3][i].addr_read = -1; > env->tlb_table[3][i].addr_write = -1; > env->tlb_table[3][i].addr_code = -1; > #endif > +#if (NB_MMU_MODES >= 5) > + env->tlb_table[4][i].addr_read = -1; > + env->tlb_table[4][i].addr_write = -1; > + env->tlb_table[4][i].addr_code = -1; > #endif > + > } > > memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); > @@ -1785,9 +1791,12 @@ void tlb_flush_page(CPUState *env, target_ulong addr) > tlb_flush_entry(&env->tlb_table[1][i], addr); > #if (NB_MMU_MODES >= 3) > tlb_flush_entry(&env->tlb_table[2][i], addr); > -#if (NB_MMU_MODES == 4) > +#endif > +#if (NB_MMU_MODES >= 4) > tlb_flush_entry(&env->tlb_table[3][i], addr); > #endif > +#if (NB_MMU_MODES >= 5) > + tlb_flush_entry(&env->tlb_table[4][i], addr); > #endif > > tlb_flush_jmp_cache(env, addr); > @@ -1871,10 +1880,14 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, > #if (NB_MMU_MODES >= 3) > for(i = 0; i < CPU_TLB_SIZE; i++) > tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); > -#if (NB_MMU_MODES == 4) > +#endif > +#if (NB_MMU_MODES >= 4) > for(i = 0; i < CPU_TLB_SIZE; i++) > tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); > #endif > +#if (NB_MMU_MODES >= 5) > + for(i = 0; i < CPU_TLB_SIZE; i++) > + tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length); > #endif > } > } > @@ -1920,10 +1933,14 @@ void cpu_tlb_update_dirty(CPUState *env) > #if (NB_MMU_MODES >= 3) > for(i = 0; i < CPU_TLB_SIZE; i++) > tlb_update_dirty(&env->tlb_table[2][i]); > -#if (NB_MMU_MODES == 4) > +#endif > +#if (NB_MMU_MODES >= 4) > for(i = 0; i < CPU_TLB_SIZE; i++) > tlb_update_dirty(&env->tlb_table[3][i]); > #endif > +#if (NB_MMU_MODES >= 5) > + for(i = 0; i < CPU_TLB_SIZE; i++) > + tlb_update_dirty(&env->tlb_table[4][i]); > #endif > } > > @@ -1945,9 +1962,12 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) > tlb_set_dirty1(&env->tlb_table[1][i], vaddr); > #if (NB_MMU_MODES >= 3) > tlb_set_dirty1(&env->tlb_table[2][i], vaddr); > -#if (NB_MMU_MODES == 4) > +#endif > +#if (NB_MMU_MODES >= 4) > tlb_set_dirty1(&env->tlb_table[3][i], vaddr); > #endif > +#if (NB_MMU_MODES >= 5) > + tlb_set_dirty1(&env->tlb_table[4][i], vaddr); > #endif > } > > diff --git a/softmmu_exec.h b/softmmu_exec.h > index 9cc4535..a43e621 100644 > --- a/softmmu_exec.h > +++ b/softmmu_exec.h > @@ -60,6 +60,7 @@ > #include "softmmu_header.h" > #undef ACCESS_TYPE > #undef MEMSUFFIX > +#endif /* (NB_MMU_MODES >= 3) */ > > #if (NB_MMU_MODES >= 4) > > @@ -78,12 +79,30 @@ > #include "softmmu_header.h" > #undef ACCESS_TYPE > #undef MEMSUFFIX > +#endif /* (NB_MMU_MODES >= 4) */ > > -#if (NB_MMU_MODES > 4) > -#error "NB_MMU_MODES > 4 is not supported for now" > -#endif /* (NB_MMU_MODES > 4) */ > -#endif /* (NB_MMU_MODES == 4) */ > -#endif /* (NB_MMU_MODES >= 3) */ > +#if (NB_MMU_MODES >= 5) > + > +#define ACCESS_TYPE 4 > +#define MEMSUFFIX MMU_MODE4_SUFFIX > +#define DATA_SIZE 1 > +#include "softmmu_header.h" > + > +#define DATA_SIZE 2 > +#include "softmmu_header.h" > + > +#define DATA_SIZE 4 > +#include "softmmu_header.h" > + > +#define DATA_SIZE 8 > +#include "softmmu_header.h" > +#undef ACCESS_TYPE > +#undef MEMSUFFIX > +#endif /* (NB_MMU_MODES >= 5) */ > + > +#if (NB_MMU_MODES > 5) > +#error "NB_MMU_MODES > 5 is not supported for now" > +#endif /* (NB_MMU_MODES > 5) */ > > /* these access are slower, they must be as rare as possible */ > #define ACCESS_TYPE (NB_MMU_MODES) > -- > 1.6.2 > > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net