From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1LrJDa-0001ZX-3x for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:52:30 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1LrJDZ-0001Z6-HO for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:52:29 -0400 Received: from [199.232.76.173] (port=50143 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1LrJDZ-0001Yz-CM for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:52:29 -0400 Received: from hall.aurel32.net ([88.191.82.174]:59462) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1LrJDY-0003lN-P2 for qemu-devel@nongnu.org; Tue, 07 Apr 2009 17:52:29 -0400 Received: from volta.aurel32.net ([2002:52e8:2fb:1:21e:8cff:feb0:693b]) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1LrJDX-0003Eg-8k for qemu-devel@nongnu.org; Tue, 07 Apr 2009 23:52:27 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1LrJDV-00035B-66 for qemu-devel@nongnu.org; Tue, 07 Apr 2009 23:52:25 +0200 Date: Tue, 7 Apr 2009 23:52:25 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations. Message-ID: <20090407215225.GG23682@volta.aurel32.net> References: <1238423794-25455-10-git-send-email-gingold@adacore.com> <1238423794-25455-11-git-send-email-gingold@adacore.com> <1238423794-25455-12-git-send-email-gingold@adacore.com> <1238423794-25455-13-git-send-email-gingold@adacore.com> <1238423794-25455-14-git-send-email-gingold@adacore.com> <1238423794-25455-15-git-send-email-gingold@adacore.com> <1238423794-25455-16-git-send-email-gingold@adacore.com> <1238423794-25455-17-git-send-email-gingold@adacore.com> <1238423794-25455-18-git-send-email-gingold@adacore.com> <1238423794-25455-19-git-send-email-gingold@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1238423794-25455-19-git-send-email-gingold@adacore.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Mon, Mar 30, 2009 at 04:36:33PM +0200, Tristan Gingold wrote: > Allow privilegied pal_code only in kernel mode. > > Signed-off-by: Tristan Gingold > --- > target-alpha/translate.c | 30 +++++++++++++++++++++++------- > 1 files changed, 23 insertions(+), 7 deletions(-) > > diff --git a/target-alpha/translate.c b/target-alpha/translate.c > index 061cf5f..6938b5d 100644 > --- a/target-alpha/translate.c > +++ b/target-alpha/translate.c > @@ -52,6 +52,7 @@ struct DisasContext { > int pal_mode; > #endif > uint32_t amask; > + uint32_t implver; > }; > > /* global register indexes */ > @@ -103,6 +104,20 @@ static void alpha_translate_init(void) > done_init = 1; > } > > +static inline int get_mxcr_iprn(DisasContext *ctx, uint32_t insn) > +{ > + switch (ctx->implver) { > + case IMPLVER_2106x: > + return insn & 0xff; > + case IMPLVER_21164: > + return insn & 0xffff; > + case IMPLVER_21264: > + return (insn >> 8) & 0xff; > + default: > + abort(); > + } > +} > + > static always_inline void gen_excp (DisasContext *ctx, > int exception, int error_code) > { > @@ -689,7 +704,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) > #if !defined (CONFIG_USER_ONLY) > } else if (palcode < 0x40) { > /* Privileged PAL code */ > - if (ctx->mem_idx & 1) > + if (ctx->mem_idx != MMU_KERNEL_IDX) > goto invalid_opc; > else > gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); > @@ -1748,7 +1763,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) > if (!ctx->pal_mode) > goto invalid_opc; > if (ra != 31) { > - TCGv tmp = tcg_const_i32(insn & 0xFF); > + TCGv tmp = tcg_const_i32(get_mxcr_iprn(ctx, insn)); > gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); > tcg_temp_free(tmp); > } > @@ -2063,9 +2078,9 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) > if (!ctx->pal_mode) > goto invalid_opc; > else { > - TCGv tmp1 = tcg_const_i32(insn & 0xFF); > - if (ra != 31) > - gen_helper_mtpr(tmp1, cpu_ir[ra]); > + TCGv tmp1 = tcg_const_i32(get_mxcr_iprn(ctx, insn)); > + if (rb != 31) > + gen_helper_mtpr(tmp1, cpu_ir[rb]); > else { > TCGv tmp2 = tcg_const_i64(0); > gen_helper_mtpr(tmp1, tmp2); > @@ -2089,7 +2104,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) > } else { > TCGv tmp; > > - if (ra != 31) { > + if (rb != 31) { > tmp = tcg_temp_new(); > tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); > } else > @@ -2097,7 +2112,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) > gen_helper_hw_ret(tmp); > tcg_temp_free(tmp); > } > - ret = 2; > + ret = 3; > break; > #endif > case 0x1F: > @@ -2352,6 +2367,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, > gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; > ctx.pc = pc_start; > ctx.amask = env->amask; > + ctx.implver = env->implver; > #if defined (CONFIG_USER_ONLY) > ctx.mem_idx = 0; > #else implver is defined once at init time, and I don't expect it to change once qemu has been started. Therefore I think there is no need to copy env->implver into ctx.implver, env->implver can be accessed directly, even from translate.c -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net