[Qemu-devel] [PATCH 3/16] S3C SDRAM memory controller Peripheral

[Vincent Sanders <vince@kyllikki.org>]

Peripheral driver for S3C SOC SDRAM controller.
Signed-off-by: Vincent Sanders <vince@simtec.co.uk>
---
 s3c24xx_memc.c |   70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff -urN qemusvnclean/hw/s3c24xx_memc.c qemusvnpatches/hw/s3c24xx_memc.c
--- qemusvnclean/hw/s3c24xx_memc.c	1970-01-01 01:00:00.000000000 +0100
+++ qemusvnpatches/hw/s3c24xx_memc.c	2009-04-23 15:57:46.000000000 +0100
@@ -0,0 +1,70 @@
+/* hw/s3c24xx_memc.c
+ *
+ * Samsung S3C24XX memory controller emulation.
+ *
+ * The SDRAM controller on several S3C SOC is generic, the emulation needs to
+ * be little more than backing the registers.
+ *
+ * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+static void
+s3c24xx_memc_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ & 0x3f) >> 2;
+
+    if (addr < 0 || addr > 12) 
+        addr = 12;
+
+    soc->memc_reg[addr] = value;
+}
+
+static uint32_t
+s3c24xx_memc_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ & 0x3f) >> 2;
+
+    if (addr < 0 || addr > 12) 
+        addr = 12;
+
+    return soc->memc_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_memc_read[] = {
+    &s3c24xx_memc_read_f,
+    &s3c24xx_memc_read_f,
+    &s3c24xx_memc_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_memc_write[] = {
+    &s3c24xx_memc_write_f,
+    &s3c24xx_memc_write_f,
+    &s3c24xx_memc_write_f,
+};
+
+
+void
+s3c24xx_memc_init(S3CState *soc, target_phys_addr_t base_addr)
+{
+    /* Memory controller is simple SDRAM control. As SDRAM is emulated and
+     * requires no setup the emulation needs to be nothing more than memory
+     * backing the registers.
+     *
+     * There are 13 registers, each 4 bytes.
+     */
+    int tag;
+    tag = cpu_register_io_memory(0, s3c24xx_memc_read, s3c24xx_memc_write, soc);
+    cpu_register_physical_memory(base_addr, 13 * 4, tag);
+  
+    for (tag = 0; tag < 13; tag++)
+        soc->memc_reg[tag] = 0;
+}


-- 
Regards Vincent
http://www.kyllikki.org/