From: Stefan Roese <sr@denx.de>
To: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH] PowerPC 44x: ibm4xx_denali_fixup_memsize fix
Date: Fri, 24 Apr 2009 06:23:16 +0200 [thread overview]
Message-ID: <200904240623.16639.sr@denx.de> (raw)
In-Reply-To: <20090423205506.GA2962@ru.mvista.com>
On Thursday 23 April 2009, Valentine Barshak wrote:
> Some U-Boot versions incorrectly set the number of chipselects to two
> for Sequoia/Rainier boards while they only have one chipselect hardwired.
> This patch adds a workaround for this, hardcoding the number of chipselects
> to one for sequioa/rainer board models and reading the actual value from
> the memory controller register DDR0_10 otherwise.
> It also fixes another error in the way ibm4xx_denali_fixup_memsize
> calculates memory size. When testing the DDR_REDUC bit, the polarity is
> backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit
> wide memory.
>
> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> Signed-off-by: Steven A. Falco <sfalco@harris.com>
Acked-by: Stefan Roese <sr@denx.de>
Thanks.
Best regards,
Stefan
prev parent reply other threads:[~2009-04-24 4:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-04-23 13:36 [PATCH] PPC440EPx SDRAM width Steven A. Falco
2009-04-23 13:45 ` Josh Boyer
2009-04-23 14:05 ` Stefan Roese
2009-04-23 14:40 ` Valentine Barshak
2009-04-23 14:59 ` Josh Boyer
2009-04-23 15:16 ` Valentine Barshak
2009-04-23 16:00 ` Steven A. Falco
2009-04-23 17:12 ` [PATCH] PowerPC: 440EPx/GRx Sequoia/Rainier U-Boot incorrect chipselect number workaround Valentine Barshak
2009-04-23 17:45 ` Steven A. Falco
2009-04-23 20:04 ` Valentine
2009-04-23 20:07 ` Josh Boyer
2009-04-23 20:12 ` Steven A. Falco
2009-04-23 20:55 ` [PATCH] PowerPC 44x: ibm4xx_denali_fixup_memsize fix Valentine Barshak
2009-04-24 4:23 ` Stefan Roese [this message]
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