Re: [PATCH 0/3] x86: adapt CPU topology detection for AMD Magny-Cours

[Andreas Herrmann <andreas.herrmann3@amd.com>]

On Mon, May 04, 2009 at 07:33:30PM +0200, Andreas Herrmann wrote:
> Hi,
> 
> Following patches add support for AMD Magny-Cours CPU.
> 
> I slightly change struct cpuinfo where I'd like to introduce
> cpu_node_id to reflect CPU topology for AMD Magny-Cours CPU which
> consists of two internal-nodes.
> 
> For all cores on the same multi-node CPU (Magny-Cours) /proc/cpuinfo
> will show:
> - same phys_proc_id
> - cpu_node_id of the internal node (0 or 1)
> - cpu_core_id (e.g. in range of 0 to 5)
> 
> I also change identification of core siblings (and thread siblings)
> which will also be based on cpu_node_id in addition to phys_proc_id.
> 
> Furthermore I adapt the L3 cache information to reflect the cache
> characteristics of one internal node instead of the entire package.
> 
> Primarily this changes are needed to correct core sibling information
> for Magny-Cours. This CPU has two NBs on one physical package -- each
> internal node has its own processor configuration space (i.e. set of
> northbridge PCI functions).

I should have mentioned that first two patches fix topology information
provided in /sys/devices/cpu/cpuX/topology (core_sibling information).

I think, the internal node information should also be exposed
there. E.g. introducing cpu_node_siblings and cpu_node_sibling_list.

But that affects other architectures (the code in
drivers/base/topology is not x86-specific) and probably needs some
more discussion. Patches to address this will follow.



Regards,
Andreas

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