From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR Date: Tue, 12 May 2009 23:41:40 +0100 Message-ID: <200905122341.40706.paul@codesourcery.com> References: <1242167590.4788.20.camel@2710p.home> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Cc: Alex Williamson , kvm-devel To: qemu-devel@nongnu.org Return-path: Received: from mail.codesourcery.com ([65.74.133.4]:49031 "EHLO mail.codesourcery.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752395AbZELWlm (ORCPT ); Tue, 12 May 2009 18:41:42 -0400 In-Reply-To: <1242167590.4788.20.camel@2710p.home> Content-Disposition: inline Sender: kvm-owner@vger.kernel.org List-ID: On Tuesday 12 May 2009, Alex Williamson wrote: > Bit 0 is the enable bit, which we not only don't want to set, but > it will stick and make us think it's an I/O port resource. Why is the ROM slot special? Doesn't the same apply to all BARs? Paul From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M40fW-00033p-Kl for qemu-devel@nongnu.org; Tue, 12 May 2009 18:41:50 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M40fS-000338-6r for qemu-devel@nongnu.org; Tue, 12 May 2009 18:41:50 -0400 Received: from [199.232.76.173] (port=34139 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M40fS-000335-16 for qemu-devel@nongnu.org; Tue, 12 May 2009 18:41:46 -0400 Received: from mx20.gnu.org ([199.232.41.8]:50357) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M40fR-0004hF-MN for qemu-devel@nongnu.org; Tue, 12 May 2009 18:41:45 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1M40fQ-0001Dw-GH for qemu-devel@nongnu.org; Tue, 12 May 2009 18:41:44 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] bios: Use the correct mask to size the PCI option ROM BAR Date: Tue, 12 May 2009 23:41:40 +0100 References: <1242167590.4788.20.camel@2710p.home> In-Reply-To: <1242167590.4788.20.camel@2710p.home> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200905122341.40706.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm-devel , Alex Williamson On Tuesday 12 May 2009, Alex Williamson wrote: > Bit 0 is the enable bit, which we not only don't want to set, but > it will stick and make us think it's an I/O port resource. Why is the ROM slot special? Doesn't the same apply to all BARs? Paul