From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] [PATCH] qemu: msi irq allocation api Date: Thu, 21 May 2009 17:07:11 +0300 Message-ID: <20090521140711.GJ25309@redhat.com> References: <20090520162130.GA22109@redhat.com> <200905211423.20843.paul@codesourcery.com> <20090521134650.GI25309@redhat.com> <200905211453.14691.paul@codesourcery.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Avi Kivity , qemu-devel@nongnu.org, Carsten Otte , kvm@vger.kernel.org, Rusty Russell , virtualization@lists.linux-foundation.org, Christian Borntraeger To: Paul Brook Return-path: Received: from mx2.redhat.com ([66.187.237.31]:37353 "EHLO mx2.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754965AbZEUOKg (ORCPT ); Thu, 21 May 2009 10:10:36 -0400 Content-Disposition: inline In-Reply-To: <200905211453.14691.paul@codesourcery.com> Sender: kvm-owner@vger.kernel.org List-ID: On Thu, May 21, 2009 at 02:53:14PM +0100, Paul Brook wrote: > > > which is a trivial wrapper around stl_phys. > > > > OK, but I'm adding another level of indirection in the middle, > > to allow us to tie in a kvm backend. > > kvm has no business messing with the PCI device code. Yes it has :) kvm needs data on MSI entries: that's the interface current kernel exposes for injecting these interrupts. I think we also need to support in-kernel devices which would inject MSI interrupt directly from kernel. For these, kvm would need to know when mask bit changes and give us info on pending bit. That's a fair amount of PCI specific code in kvm. -- MST