From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 23 May 2009 02:22:50 +0200 Subject: [U-Boot] [PATCH 1/7] mx27: basic cpu support In-Reply-To: <1242777361-6717-2-git-send-email-yanok@emcraft.com> References: <1242777361-6717-1-git-send-email-yanok@emcraft.com> <1242777361-6717-2-git-send-email-yanok@emcraft.com> Message-ID: <20090523002250.GA20889@game.jcrosoft.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > diff --git a/cpu/arm926ejs/mx27/interrupt.c b/cpu/arm926ejs/mx27/interrupt.c please rename it timer.c > new file mode 100644 > index 0000000..8f3e809 > --- /dev/null > +++ b/cpu/arm926ejs/mx27/interrupt.c > @@ -0,0 +1,201 @@ > +/* > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH > + * Marius Groeger > + * > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH > + * Alex Zuepke > + * > + * (C) Copyright 2002 > + * Gary Jennejohn, DENX Software Engineering, > + * > + * (C) Copyright 2009 > + * Ilya Yanok, Emcraft Systems Ltd, > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + > +/* > + * Reset the cpu by setting up the watchdog timer and let it time out > + */ > +void reset_cpu (ulong ignored) please move to a reset.c file > +{ > + struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; > + /* Disable watchdog and set Time-Out field to 0 */ > + writel(0x00000000, ®s->WCR); > + > + /* Write Service Sequence */ > + writel(0x00005555, ®s->WSR); > + writel(0x0000AAAA, ®s->WSR); > + > + /* Enable watchdog */ > + writel(WCR_WDE, ®s->WCR); > + > + while (1); > + /*NOTREACHED*/ > +} > diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h > new file mode 100644 > index 0000000..497afe5 > --- /dev/null > +++ b/include/asm-arm/arch-mx27/asm-offsets.h please add GPL header and copyright > @@ -0,0 +1,16 @@ > +#define AIPI1_PSR0 0x10000000 > +#define AIPI1_PSR1 0x10000004 > +#define AIPI2_PSR0 0x10020000 > +#define AIPI2_PSR1 0x10020004 > +#define CSCR 0x10027000 > +#define MPCTL0 0x10027004 > +#define SPCTL0 0x1002700c > +#define PCDR0 0x10027018 > +#define PCDR1 0x1002701c > +#define PCCR0 0x10027020 > +#define PCCR1 0x10027024 > +#define ESDCTL0_ROF 0x00 > +#define ESDCFG0_ROF 0x04 > +#define ESDCTL1_ROF 0x08 > +#define ESDCFG1_ROF 0x0C > +#define ESDMISC_ROF 0x10 > diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h > new file mode 100644 > index 0000000..f6615d9 > --- /dev/null > +++ b/include/asm-arm/arch-mx27/clock.h > @@ -0,0 +1,17 @@ please add GPL header and copyright > + > +#ifndef __ASM_ARCH_CLOCK_H > +#define __ASM_ARCH_CLOCK_H > +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); > + > +ulong imx_get_mpllclk(void); > +ulong imx_get_armclk(void); > +ulong imx_get_spllclk(void); > +ulong imx_get_fclk(void); > +ulong imx_get_hclk(void); > +ulong imx_get_bclk(void); > +ulong imx_get_perclk1(void); > +ulong imx_get_perclk2(void); > +ulong imx_get_perclk3(void); > +ulong imx_get_ahbclk(void); > + > +#endif /* __ASM_ARCH_CLOCK_H */ > diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h > new file mode 100644 > index 0000000..16d2142 > --- /dev/null > +++ b/include/asm-arm/arch-mx27/imx-regs.h > @@ -0,0 +1,508 @@ > +/* > + * > + * (c) 2007 Pengutronix, Sascha Hauer > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef _IMX_REGS_H > +#define _IMX_REGS_H > + > +#ifndef __ASSEMBLY__ > + > +extern void imx_gpio_mode (int gpio_mode); > + > +/* AIPI */ > +struct aipi_regs { > + u32 PSR0; please do not use uppercase > + u32 PSR1; > +}; > + > +/* System Control */ > +struct system_control_regs { > + u32 res[5]; > + u32 FMCR; > + u32 GPCR; > + u32 WBCR; > + u32 DSCR1; > + u32 DSCR2; > + u32 DSCR3; > + u32 DSCR4; > + u32 DSCR5; > + u32 DSCR6; > + u32 DSCR7; > + u32 DSCR8; > + u32 DSCR9; > + u32 DSCR10; > + u32 DSCR11; > + u32 DSCR12; > + u32 DSCR13; > + u32 PSCR; > + u32 PMCR; > + u32 res1; > + u32 DCVR0; > + u32 DCVR1; > + u32 DCVR2; > + u32 DCVR3; > +}; > + > +/* Chip Select Registers */ > +struct weim_regs { > + u32 CS0U; /* Chip Select 0 Upper Register */ ^^^^ whitespace please fix and please check the other comments > + u32 CS0L; /* Chip Select 0 Lower Register */ > + u32 CS0A; /* Chip Select 0 Addition Register */ + > +/* FMCR System Control bit definition*/ > +#define UART4_RXD_CTL (1<<25) please add space before and after '<<' > +#define UART4_RTS_CTL (1<<24) > +#define KP_COL6_CTL (1<<18) > +#define KP_ROW7_CTL (1<<17) > +#define KP_ROW6_CTL (1<<16) > +#define PC_WAIT_B_CTL (1<<14) > +#define PC_READY_CTL (1<<13) > +#define PC_VS1_CTL (1<<12) > +#define PC_VS2_CTL (1<<11) > +#define PC_BVD1_CTL (1<<10) > +#define PC_BVD2_CTL (1<<9) > +#define IOS16_CTL (1<<8) > +#define NF_FMS (1<<5) > +#define NF_16BIT_SEL (1<<4) > +#define SLCDC_SEL (1<<2) > +#define SDCS1_SEL (1<<1) > +#define SDCS0_SEL (1<<0) > + Best Regards, J.