From: Andreas Herrmann <andreas.herrmann3@amd.com>
To: Ingo Molnar <mingo@elte.hu>, "H. Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] x86: cacheinfo: fixup L3 cache information for AMD multi-node processors
Date: Fri, 29 May 2009 20:49:43 +0200 [thread overview]
Message-ID: <20090529184943.GG23770@alberich.amd.com> (raw)
In-Reply-To: <20090529184023.GD23770@alberich.amd.com>
L3 cache size, associativity and shared_cpu information need to be
adapted to show information for an internal node instead of the
entire physical package.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 22 +++++++++++++++++-----
1 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 789efe2..dbafe2b 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -241,7 +241,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 0:
if (!l1->val)
return;
- assoc = l1->assoc;
+ assoc = assocs[l1->assoc];
line_size = l1->line_size;
lines_per_tag = l1->lines_per_tag;
size_in_kb = l1->size_in_kb;
@@ -249,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 2:
if (!l2.val)
return;
- assoc = l2.assoc;
+ assoc = assocs[l2.assoc];
line_size = l2.line_size;
lines_per_tag = l2.lines_per_tag;
/* cpu_data has errata corrections for K7 applied */
@@ -258,10 +258,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
case 3:
if (!l3.val)
return;
- assoc = l3.assoc;
+ assoc = assocs[l3.assoc];
line_size = l3.line_size;
lines_per_tag = l3.lines_per_tag;
size_in_kb = l3.size_encoded * 512;
+ if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
+ size_in_kb = size_in_kb >> 1;
+ assoc = assoc >> 1;
+ }
break;
default:
return;
@@ -278,10 +282,10 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
- if (assoc == 0xf)
+ if (assoc == 0xffff)
eax->split.is_fully_associative = 1;
ebx->split.coherency_line_size = line_size - 1;
- ebx->split.ways_of_associativity = assocs[assoc] - 1;
+ ebx->split.ways_of_associativity = assoc - 1;
ebx->split.physical_line_partition = lines_per_tag - 1;
ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
(ebx->split.ways_of_associativity + 1) - 1;
@@ -598,7 +602,15 @@ static void __cpuinit get_cpu_leaves(void *_retval)
cache_remove_shared_cpu_map(cpu, i);
break;
}
+#ifdef CONFIG_MULTI_NODE_CPU
+ if (boot_cpu_has(X86_FEATURE_AMD_DCM))
+ cpumask_copy(to_cpumask(this_leaf->shared_cpu_map),
+ topology_cpu_node_cpumask(cpu));
+ else
+ cache_shared_cpu_map_setup(cpu, j);
+#else
cache_shared_cpu_map_setup(cpu, j);
+#endif
}
}
--
1.6.3.1
prev parent reply other threads:[~2009-05-29 18:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-29 18:40 [PATCH 0/3 v2] x86: adapt CPU topology detection for AMD Magny-Cours Andreas Herrmann
2009-05-29 18:42 ` [PATCH 1/3] x86: provide CPU topology information for multi-node processors Andreas Herrmann
2009-06-02 15:05 ` Bert Wesarg
2009-06-02 15:58 ` Andreas Herrmann
2009-06-02 16:19 ` Bert Wesarg
2009-05-29 18:48 ` [PATCH 2/3] x86: add topology detection for AMD " Andreas Herrmann
2009-05-29 18:49 ` Andreas Herrmann [this message]
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