From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ira W. Snyder <iws@ovro.caltech.edu>
Date: Wed, 8 Jul 2009 16:02:31 -0700
Subject: [U-Boot] [PATCH 0/3] DMA ECC update
In-Reply-To: <20090708223129.GF2827@ovro.caltech.edu>
References: <1247081322-22392-1-git-send-email-ptyser@xes-inc.com>
	<20090708223129.GF2827@ovro.caltech.edu>
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On Wed, Jul 08, 2009 at 03:31:29PM -0700, Ira W. Snyder wrote:
> On Wed, Jul 08, 2009 at 02:28:39PM -0500, Peter Tyser wrote:
> > These changes bring the 83xx SDRAM ECC initialization in line
> > with the 85xx/86xx boards and also fixes a minor bug in fsl_dma.c.
> > 
> > I don't have any 83xx boards to test on, so it would be appreciated
> > if someone with 83xx hardware that uses ECC could give the patches
> > a shot.
> > 
> > It'd be nice if SDRAM could be initialized via the DDR controller
> > with CONFIG_ECC_INIT_VIA_DDRCONTROLLER on the 83xx platform too,
> > but I'm not going to tackle it:)
> > 
> > The patches also resolve the compile error Stefan brought up with
> > non-freescale boards with CONFIG_ECC.
> > 
> > Peter Tyser (3):
> >   83xx: Default to using DMA to initialize SDRAM
> >   83xx: Added CONFIG_MEM_INIT_VALUE for boards with ECC
> >   fsl_dma: Fix SDRAM initial value
> > 
> 
> Something in this patch makes the ECC DDR initialization VERY slow. It
> used to take <5 seconds, now it takes ~20 seconds for the memory to
> initialize.
> 
> I wonder why the CPU method would be so much faster?
> 

As a further quick note, I just hacked in support for initializing the
DDR via the DDR controller. Nothing good for submission, but it works
fine for my board. (We're using fixed_sdram(), no SPD code).

The DDR controller takes about 3 seconds to initialize all 256MB of RAM
on the board.

Ira