From: jamie@shareable.org (Jamie Lokier)
To: linux-arm-kernel@lists.infradead.org
Subject: LDREX/STREX and pre-emption on *non*-SMP hardware
Date: Mon, 14 Sep 2009 02:44:04 +0100 [thread overview]
Message-ID: <20090914014404.GE30621@shareable.org> (raw)
In-Reply-To: <1252877053.16083.5.camel@pc1117.cambridge.arm.com>
Catalin Marinas wrote:
> > But what about a single CPU system?
>
> With two or more threads, you can have something like below, even on UP
> systems:
>
> T1 T2
> LDREX
> LDREX
> STREX (succeeds)
> LDREX
> STREX (succeeds)
> STREX (fails)
>
> Thread T2 perform two successive atomic modifications but the context
> switch happens during the second one, so STREX in T1 should not succeed.
That's very convincing, and you are right of course. Thanks!
-- Jamie
prev parent reply other threads:[~2009-09-14 1:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-13 19:49 LDREX/STREX and pre-emption on *non*-SMP hardware Jamie Lokier
2009-09-13 21:24 ` Catalin Marinas
2009-09-14 1:44 ` Jamie Lokier [this message]
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