From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Brown Subject: Re: WM8731 using I2S on omap3 McBSP2 issues Date: Mon, 28 Sep 2009 17:13:45 +0100 Message-ID: <20090928161345.GD32420@sirena.org.uk> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cassiel.sirena.org.uk (cassiel.sirena.org.uk [80.68.93.111]) by alsa0.perex.cz (Postfix) with ESMTP id 130CC243EE for ; Mon, 28 Sep 2009 18:13:47 +0200 (CEST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: alsa-devel-bounces@alsa-project.org Errors-To: alsa-devel-bounces@alsa-project.org To: Rick Bronson Cc: alsa-devel@alsa-project.org, Peter Ujfalusi List-Id: alsa-devel@alsa-project.org On Mon, Sep 28, 2009 at 09:07:26AM -0700, Rick Bronson wrote: > I don't believe it's possible for me to try the master/slave switch. > Please take a look at http://www.efn.org/~rick/pub/wm8731.jpg Note > that DACLRC and ADCLRC are connected. This requires me to run as > slave, right? Our bit clock line is buffered so I don't think that > will be a problem. Tying the DAC and ADC LRCLKs together should be fine in either master or slave mode, I'd expect (but I am not a hardware engineer).