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From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Octeon: Use lockless interrupt controller operations when possible.
Date: Tue, 13 Oct 2009 21:41:55 +0200	[thread overview]
Message-ID: <20091013194155.GA727@linux-mips.org> (raw)
In-Reply-To: <1255458363-8987-1-git-send-email-ddaney@caviumnetworks.com>

On Tue, Oct 13, 2009 at 11:26:03AM -0700, David Daney wrote:

> Some newer Octeon chips have registers that allow lockless operation
> of the interrupt controller.  Take advantage of them.

Thanks, applied.

  Ralf

      reply	other threads:[~2009-10-13 19:40 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-10-13 15:51 [PATCH 0/2] Two improvements to Octeon irq handling David Daney
2009-10-13 15:52 ` [PATCH 1/2] MIPS: Octeon: Use write_lock_irqsave/write_unlock_irqrestore when setting irq affinity David Daney
2009-10-13 16:17   ` Ralf Baechle
2009-10-13 15:52 ` [PATCH 2/2] MIPS: Octeon: Use lockless interrupt controller operations when possible David Daney
2009-10-13 16:20   ` Ralf Baechle
2009-10-13 18:26     ` [PATCH] " David Daney
2009-10-13 19:41       ` Ralf Baechle [this message]

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