Re: [Qemu-devel] [PATCH 01/18] Use tcg_global_mem_new_i32 to allocate ARM registers in TCG.

[Aurelien Jarno <aurelien@aurel32.net>]

On Sun, Jul 19, 2009 at 03:33:15PM +0000, Filip Navara wrote:
> Currently each read/write of ARM register involves a LD/ST TCG operation. This
> patch uses TCG memory-backed registers to represent the ARM register set. With
> memory-backed registers the LD/ST operations are transparently generated by TCG
> and host registers could be used to optimize the generated code.
> 
> Signed-off-by: Filip Navara <filip.navara@gmail.com>
> ---
>  target-arm/translate.c |   40 +++++++++++++++++++++++-----------------
>  1 files changed, 23 insertions(+), 17 deletions(-)
> 
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index c32e7f9..a0c0436 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -76,6 +76,7 @@ typedef struct DisasContext {
>  static TCGv_ptr cpu_env;
>  /* We reuse the same 64-bit temporaries for efficiency.  */
>  static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
> +static TCGv_i32 cpu_R[16];
>  
>  /* FIXME:  These should be removed.  */
>  static TCGv cpu_T[2];
> @@ -85,14 +86,26 @@ static TCGv_i64 cpu_F0d, cpu_F1d;
>  #define ICOUNT_TEMP cpu_T[0]
>  #include "gen-icount.h"
>  
> +static const char *regnames[] =
> +    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> +      "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
> +
>  /* initialize TCG globals.  */
>  void arm_translate_init(void)
>  {
> +    int i;
> +
>      cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
>  
>      cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0");
>      cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1");
>  
> +    for (i = 0; i < 16; i++) {
> +        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
> +                                          offsetof(CPUState, regs[i]),
> +                                          regnames[i]);
> +    }
> +
>  #define GEN_HELPER 2
>  #include "helpers.h"
>  }
> @@ -167,7 +180,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int reg)
>              addr = (long)s->pc + 4;
>          tcg_gen_movi_i32(var, addr);
>      } else {
> -        tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
> +        tcg_gen_mov_i32(var, cpu_R[reg]);
>      }
>  }
>  
> @@ -187,7 +200,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
>          tcg_gen_andi_i32(var, var, ~1);
>          s->is_jmp = DISAS_JUMP;
>      }
> -    tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg]));
> +    tcg_gen_mov_i32(cpu_R[reg], var);
>      dead_tmp(var);
>  }
>  
> @@ -789,27 +802,22 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr)
>      TCGv tmp;
>  
>      s->is_jmp = DISAS_UPDATE;
> -    tmp = new_tmp();
>      if (s->thumb != (addr & 1)) {
> +        tmp = new_tmp();
>          tcg_gen_movi_i32(tmp, addr & 1);
>          tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
> +        dead_tmp(tmp);
>      }
> -    tcg_gen_movi_i32(tmp, addr & ~1);
> -    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15]));
> -    dead_tmp(tmp);
> +    tcg_gen_mov_i32(cpu_R[15], addr & ~1);
>  }

That should be tcg_gen_movi_i32()

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net