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From: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
To: David Miller <davem@davemloft.net>
Cc: nickpiggin@yahoo.com.au, linux-kernel@vger.kernel.org,
	paulmck@linux.vnet.ibm.com
Subject: Re: sparc64 cmpxchg is not a full memory barrier anymore ?
Date: Fri, 23 Oct 2009 08:33:27 -0400	[thread overview]
Message-ID: <20091023123327.GA14058@Krystal> (raw)
In-Reply-To: <20091022.145645.249762938.davem@davemloft.net>

* David Miller (davem@davemloft.net) wrote:
> From: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
> Date: Thu, 22 Oct 2009 14:32:42 -0400
> 
> > The same applies to the other atomic instructions we find in this list.
> > How is the correct ordering of loads wrt to cmxchg (and other atomic
> > ops) still ensured by this modification?
> 
> All actual sparc64 chips implement more strict ordering than
> the V9 specification permits.  The memory barriers were just
> nops and actually not doing anything more than the chip
> already does for us.

OK. Perhaps adding a comment to that effect near sparc mb()
implementation would be appropriate ?

Thanks,

Mathieu


-- 
Mathieu Desnoyers
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68

  reply	other threads:[~2009-10-23 12:33 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-10-22 18:32 sparc64 cmpxchg is not a full memory barrier anymore ? Mathieu Desnoyers
2009-10-22 19:57 ` Sparc64 support added to Userspace RCU Mathieu Desnoyers
2009-11-16  4:31   ` David Miller
2009-11-16 20:27     ` Mathieu Desnoyers
2009-10-22 21:56 ` sparc64 cmpxchg is not a full memory barrier anymore ? David Miller
2009-10-23 12:33   ` Mathieu Desnoyers [this message]
2009-10-23 14:19     ` David Miller

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