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From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] NAND: Update to support 64 bit device size
Date: Thu, 5 Nov 2009 16:32:16 -0600	[thread overview]
Message-ID: <20091105223216.GA13337@loki.buserror.net> (raw)
In-Reply-To: <1256925083-385-1-git-send-email-s-paulraj@ti.com>

On Fri, Oct 30, 2009 at 01:51:23PM -0400, s-paulraj at ti.com wrote:
> From: Sandeep Paulraj <s-paulraj@ti.com>
> 
> This patch adds support for NANDs greater than 2 GB.
> Patch is based on the MTD NAND driver in the kernel.
> 
> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Applied to u-boot-nand-flash/next, with a few whitespace changes that make
it more like the upstream code (though it's still not identical, as upstream
has some long lines that got wrapped in U-Boot).  In particular, some things
were double-tabbed, and existing alignment broken.

Here's the diff from the posted patch to what was applied:

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 6848f28..30a3e9e 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2218,8 +2218,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 	loff_t len;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
-			"len = %llu\n", (unsigned long long) instr->addr,
-			(unsigned long long) instr->len);
+		 "len = %llu\n", (unsigned long long) instr->addr,
+		 (unsigned long long) instr->len);
 
 	/* Start address must align on block boundary */
 	if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
@@ -2324,9 +2324,9 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		 * page being erased
 		 */
 		if (bbt_masked_page != 0xffffffff &&
-			(page & BBT_PAGE_MASK) == bbt_masked_page)
-				rewrite_bbt[chipnr] = ((loff_t)page <<
-							chip->page_shift);
+		    (page & BBT_PAGE_MASK) == bbt_masked_page)
+			rewrite_bbt[chipnr] =
+				((loff_t)page << chip->page_shift);
 
 		/* Increment page address and decrement length */
 		len -= (1 << chip->phys_erase_shift);
@@ -2373,9 +2373,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 			continue;
 		/* update the BBT for chip */
 		MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
-				"(%d:0x%0llx 0x%0x)\n", chipnr,
-				rewrite_bbt[chipnr],
-				chip->bbt_td->pages[chipnr]);
+			  "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
+			  chip->bbt_td->pages[chipnr]);
 		nand_update_bbt(mtd, rewrite_bbt[chipnr]);
 	}
 
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 1167c90..2fe68ab 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -443,8 +443,8 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 		if (ret) {
 			this->bbt[i >> 3] |= 0x03 << (i & 0x6);
 			MTDDEBUG (MTD_DEBUG_LEVEL0,
-					"Bad eraseblock %d@0x%012llx\n",
-					i >> 1, (unsigned long long)from);
+				  "Bad eraseblock %d at 0x%012llx\n",
+				  i >> 1, (unsigned long long)from);
 			mtd->ecc_stats.badblocks++;
 		}
 
@@ -746,7 +746,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 
 		printk(KERN_DEBUG "Bad block table written to 0x%012llx, "
 		       "version 0x%02X\n", (unsigned long long)to,
-			td->version[chip]);
+		       td->version[chip]);
 
 		/* Mark it as used */
 		td->pages[chip] = page;

  parent reply	other threads:[~2009-11-05 22:32 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-10-30 17:51 [U-Boot] [PATCH] NAND: Update to support 64 bit device size s-paulraj at ti.com
2009-10-30 17:53 ` Paulraj, Sandeep
2009-11-05 22:32 ` Scott Wood [this message]
2009-11-05 23:11   ` Paulraj, Sandeep

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