Re: [PATCH] Enable non page boundary BAR device assignment

["Michael S. Tsirkin" <mst@redhat.com>]

On Thu, Dec 10, 2009 at 12:37:37PM +0200, Muli Ben-Yehuda wrote:
> On Thu, Dec 10, 2009 at 11:31:01AM +0100, Alexander Graf wrote:
> 
> > > What do you have in mind for such a rewrite?
> > 
> > I'd like to see it more well-abstracted and versatile. I don't see
> > an obvious reason why we shouldn't be able to use a physical device
> > in a TCG target :-).
> 
> mmio and pio are easy, DMA you'd need an IOMMU for security, or
> whatever uio does just for translation,

uio currently does not support DMA, but I plan to fix this

> and interrupts you probably
> get for free from uio. Seems eminently doable to me. Why you'd want to
> is another matter :-)
> 
> Cheers,
> Muli

The list above ignores the biggest issue: you would have to change TCG
code generation to make this work.

For example, I think a read memory barrier is currently ignored in
translation, and host CPU will reorder reads.  Some drivers might also
rely on ordering guarantees that depend on CPU cacheline sizes.  Atomics
is another bag of tricks but I expect atomics on a DMA memory are not
widely used.

I am not sure this problem is solvable unless host and guest
architectures are very similar.

-- 
MST