From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael S. Tsirkin" Subject: Re: [PATCH] Enable non page boundary BAR device assignment Date: Thu, 10 Dec 2009 13:21:40 +0200 Message-ID: <20091210112139.GA11956@redhat.com> References: <1260380334-8323-1-git-send-email-agraf@suse.de> <20091210051604.GA9049@il.ibm.com> <20091210094357.GC11028@redhat.com> <20091210102301.GC10800@il.ibm.com> <6615086C-8CA1-4AFE-A95D-3DC337375749@suse.de> <20091210103737.GG10800@il.ibm.com> <20091210105655.GE11028@redhat.com> <691C87D2-A72B-4069-B067-19209776D3CE@suse.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Muli Ben-Yehuda , kvm@vger.kernel.org To: Alexander Graf Return-path: Received: from mx1.redhat.com ([209.132.183.28]:47734 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760638AbZLJLYU (ORCPT ); Thu, 10 Dec 2009 06:24:20 -0500 Content-Disposition: inline In-Reply-To: <691C87D2-A72B-4069-B067-19209776D3CE@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: On Thu, Dec 10, 2009 at 12:09:13PM +0100, Alexander Graf wrote: > > On 10.12.2009, at 11:56, Michael S. Tsirkin wrote: > > > On Thu, Dec 10, 2009 at 12:37:37PM +0200, Muli Ben-Yehuda wrote: > >> On Thu, Dec 10, 2009 at 11:31:01AM +0100, Alexander Graf wrote: > >> > >>>> What do you have in mind for such a rewrite? > >>> > >>> I'd like to see it more well-abstracted and versatile. I don't see > >>> an obvious reason why we shouldn't be able to use a physical device > >>> in a TCG target :-). > >> > >> mmio and pio are easy, DMA you'd need an IOMMU for security, or > >> whatever uio does just for translation, > > > > uio currently does not support DMA, but I plan to fix this > > > >> and interrupts you probably > >> get for free from uio. Seems eminently doable to me. Why you'd want to > >> is another matter :-) > >> > >> Cheers, > >> Muli > > > > The list above ignores the biggest issue: you would have to change TCG > > code generation to make this work. > > > > For example, I think a read memory barrier is currently ignored in > > translation, and host CPU will reorder reads. Some drivers might also > > rely on ordering guarantees that depend on CPU cacheline sizes. Atomics > > is another bag of tricks but I expect atomics on a DMA memory are not > > widely used. > > Since we'd use the mmio callbacks for MMIO we'd be strictly ordered, no? > > Alex Not unless you issue appropriate host memory barriers on mmio callbacks (kvm currently uses a lock for this, which has an implicit barrier, but I do not think TCG does this). But even then, it depends on the device, for some devices DMA memory reads/writes might depend on each other. Look at virtio as an example, a real device might have the same semantics. As a simpler example, some devices DMA the following into ring in host memory to signal data available: - valid tag - data length host will read tag, and when it's valid use data length, but e.g. on intel this only works well if these share a cache line, otherwise data read might bypass tag read and you get invalid data. -- MST