From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NNDgT-0005Qt-GJ for qemu-devel@nongnu.org; Tue, 22 Dec 2009 17:58:29 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NNDgP-0005Po-J5 for qemu-devel@nongnu.org; Tue, 22 Dec 2009 17:58:29 -0500 Received: from [199.232.76.173] (port=34041 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NNDgP-0005Pl-Fp for qemu-devel@nongnu.org; Tue, 22 Dec 2009 17:58:25 -0500 Received: from mx20.gnu.org ([199.232.41.8]:29219) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NNDgP-0006pe-8I for qemu-devel@nongnu.org; Tue, 22 Dec 2009 17:58:25 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NNDgN-0008VN-2J for qemu-devel@nongnu.org; Tue, 22 Dec 2009 17:58:23 -0500 From: Paul Brook Date: Tue, 22 Dec 2009 22:58:16 +0000 References: <20091208161818.GA32188@redhat.com> <200912221625.33126.paul@codesourcery.com> <20091222163437.GE18676@redhat.com> In-Reply-To: <20091222163437.GE18676@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <200912222258.16458.paul@codesourcery.com> Subject: [Qemu-devel] Re: [PATCH-RFC 0/3] qemu: memory barriers in virtio List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Rusty Russell , qemu-devel@nongnu.org > > Given this is supposed to be portable code, I wonder if we should have > > atomic ordered memory accessors instead. > > > > Paul > > Could you clarify please? > > The infiniband bits I used as base are very portable, > I know they build on a ton of platforms. I just stripped > a couple of infiniband specific assumptions from there. > > Do you suggest we use __sync_synchronize? > Unfortunately this is broken or slow on many platforms. > I do use it when it seems safe or when we see a platform > we don't know about. I mean have a single function that does both the atomic load/store and the memory barrier. Instead of: stw_phys(addr, val) barrier(); We do: stw_phys_barrier(addr, val). This avoids issues in the future (multithreaded TCG) where atomic memory accesses may be nontrivial. Paul