From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Lan Tianyu <tianyu.lan@intel.com>, Wei Liu <wei.liu2@citrix.com>,
IanJackson <Ian.Jackson@eu.citrix.com>,
Xen-devel <xen-devel@lists.xen.org>,
Joao Martins <joao.m.martins@oracle.com>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: CPUID improvements (phase 2) Design Doc
Date: Wed, 9 Nov 2016 11:36:39 +0000 [thread overview]
Message-ID: <200f685f-e836-da56-7882-6dc929729d9a@citrix.com> (raw)
In-Reply-To: <5822ED0E020000780011D458@prv-mh.provo.novell.com>
On 09/11/16 08:31, Jan Beulich wrote:
>>>> On 08.11.16 at 19:36, <andrew.cooper3@citrix.com> wrote:
>> On 08/11/16 16:32, Jan Beulich wrote:
>>>>>> On 08.11.16 at 16:35, <andrew.cooper3@citrix.com> wrote:
>>>> Please find inline the design doc for further CPUID improvements, planned for
>>>> development during the 4.9 timeframe.
>>> Looks good, just a couple of minor remarks.
>>>
>>>> ## Changes in hypercall behaviour
>>>>
>>>> During domain construction, some pieces of information critical to the
>>>> determination of the domains maximum acceptable CPUID policy are available
>>>> right from the very start (Most notably, the HVM and HAP flags from the
>>>> `XEN_DOMCTL_createdomain`).
>>>>
>>>> However, some other parameters are not available at convenient points.
>>>>
>>>> 1. The disable flag from `XEN_DOMCTL_disable_migrate` is used to set
>>>> `d->disable_migrate`, whose only purpose is to avoid the unconditional
>>>> clobbering of the Invariant TSC flag. This flag cannot even be queried by
>>>> the toolstack once set.
>>>>
>>>> There are other facilities which should be restricted based on whether a
>>>> VM might migrate or not. (e.g. The use of LBR, whose record format is
>>>> hardware specific.)
>>> Not really - the LBR format only limits the set of hosts the VM can
>>> migrate to. I.e. this is just like a CPUID flag which needs to be set
>>> on the target host in order for the VM to be permitted to migrate
>>> there.
>> It is more complicated than that. The LBR format also depends on
>> whether TSX is enabled or not, which on Haswell-WS CPUs depends on
>> whether hyperthreading is enabled.
> Yes, but is this relevant? It's still only a value (identifying the format)
> which needs to match between source and destination hosts. I.e. not
> different from individual feature bits, just that here we're dealing with
> a multi-bit entity.
LBR format is controlled by IA32_PERF_CAPABILITIES[5:0], which I will
eventually get to covering with MSR levelling, with this being a
strictly non-levelable field.
Users' expectations when migrating a VM is that it should be able to go
anywhere. In practice, this is only insofar as we can maintain
compatibility. We should default to being as compatible as possible; if
a user asks for both migrateable and LBR, then thats fine as it comes
with an understanding of reduced mobility.
~Andrew
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prev parent reply other threads:[~2016-11-09 11:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-08 15:35 CPUID improvements (phase 2) Design Doc Andrew Cooper
2016-11-08 16:32 ` Jan Beulich
2016-11-08 18:36 ` Andrew Cooper
2016-11-09 8:31 ` Jan Beulich
2016-11-09 11:36 ` Andrew Cooper [this message]
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