From: Paul Walmsley <paul@pwsan.com>
To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 16/18] OMAP3 DPLL: reorganize static functions
Date: Fri, 15 Jan 2010 02:07:08 -0700 [thread overview]
Message-ID: <20100115090707.30690.33928.stgit@localhost.localdomain> (raw)
In-Reply-To: <20100115090613.30690.49355.stgit@localhost.localdomain>
Move all static functions up to the top of the file to match the
practice in other OMAP clock code. Make omap3_noncore_dpll_program()
static (noted by sparse) and prepend an underscore to the function
name to mark that it is file-local.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/dpll3xxx.c | 113 +++++++++++++++++++++-------------------
1 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f6055b4..2b559fc 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -44,17 +44,7 @@
#define MAX_DPLL_WAIT_TRIES 1000000
-
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
- return omap2_get_dpll_rate(clk);
-}
+/* Private functions */
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
@@ -136,8 +126,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
return f;
}
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
/*
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
* @clk: pointer to a DPLL struct clk
@@ -237,6 +225,63 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
return 0;
}
+/*
+ * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock.. Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+ struct dpll_data *dd = clk->dpll_data;
+ u32 v;
+
+ /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ _omap3_noncore_dpll_bypass(clk);
+
+ /* Set jitter correction */
+ if (!cpu_is_omap44xx()) {
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->freqsel_mask;
+ v |= freqsel << __ffs(dd->freqsel_mask);
+ __raw_writel(v, dd->control_reg);
+ }
+
+ /* Set DPLL multiplier, divider */
+ v = __raw_readl(dd->mult_div1_reg);
+ v &= ~(dd->mult_mask | dd->div1_mask);
+ v |= m << __ffs(dd->mult_mask);
+ v |= (n - 1) << __ffs(dd->div1_mask);
+ __raw_writel(v, dd->mult_div1_reg);
+
+ /* We let the clock framework set the other output dividers later */
+
+ /* REVISIT: Set ramp-up delay? */
+
+ _omap3_noncore_dpll_lock(clk);
+
+ return 0;
+}
+
+/* Public functions */
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+ return omap2_get_dpll_rate(clk);
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
/**
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
* @clk: pointer to a DPLL struct clk
@@ -292,48 +337,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
/* Non-CORE DPLL rate set code */
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock.. Returns -EINVAL upon error, or 0 upon success.
- */
-int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
- struct dpll_data *dd = clk->dpll_data;
- u32 v;
-
- /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
- _omap3_noncore_dpll_bypass(clk);
-
- /* Set jitter correction */
- if (!cpu_is_omap44xx()) {
- v = __raw_readl(dd->control_reg);
- v &= ~dd->freqsel_mask;
- v |= freqsel << __ffs(dd->freqsel_mask);
- __raw_writel(v, dd->control_reg);
- }
-
- /* Set DPLL multiplier, divider */
- v = __raw_readl(dd->mult_div1_reg);
- v &= ~(dd->mult_mask | dd->div1_mask);
- v |= m << __ffs(dd->mult_mask);
- v |= (n - 1) << __ffs(dd->div1_mask);
- __raw_writel(v, dd->mult_div1_reg);
-
- /* We let the clock framework set the other output dividers later */
-
- /* REVISIT: Set ramp-up delay? */
-
- _omap3_noncore_dpll_lock(clk);
-
- return 0;
-}
-
/**
* omap3_noncore_dpll_set_rate - set non-core DPLL rate
* @clk: struct clk * of DPLL to set
WARNING: multiple messages have this Message-ID (diff)
From: paul@pwsan.com (Paul Walmsley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 16/18] OMAP3 DPLL: reorganize static functions
Date: Fri, 15 Jan 2010 02:07:08 -0700 [thread overview]
Message-ID: <20100115090707.30690.33928.stgit@localhost.localdomain> (raw)
In-Reply-To: <20100115090613.30690.49355.stgit@localhost.localdomain>
Move all static functions up to the top of the file to match the
practice in other OMAP clock code. Make omap3_noncore_dpll_program()
static (noted by sparse) and prepend an underscore to the function
name to mark that it is file-local.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/dpll3xxx.c | 113 +++++++++++++++++++++-------------------
1 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f6055b4..2b559fc 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -44,17 +44,7 @@
#define MAX_DPLL_WAIT_TRIES 1000000
-
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-unsigned long omap3_dpll_recalc(struct clk *clk)
-{
- return omap2_get_dpll_rate(clk);
-}
+/* Private functions */
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
@@ -136,8 +126,6 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
return f;
}
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
/*
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
* @clk: pointer to a DPLL struct clk
@@ -237,6 +225,63 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
return 0;
}
+/*
+ * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock.. Returns -EINVAL upon error, or 0 upon success.
+ */
+static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+ struct dpll_data *dd = clk->dpll_data;
+ u32 v;
+
+ /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ _omap3_noncore_dpll_bypass(clk);
+
+ /* Set jitter correction */
+ if (!cpu_is_omap44xx()) {
+ v = __raw_readl(dd->control_reg);
+ v &= ~dd->freqsel_mask;
+ v |= freqsel << __ffs(dd->freqsel_mask);
+ __raw_writel(v, dd->control_reg);
+ }
+
+ /* Set DPLL multiplier, divider */
+ v = __raw_readl(dd->mult_div1_reg);
+ v &= ~(dd->mult_mask | dd->div1_mask);
+ v |= m << __ffs(dd->mult_mask);
+ v |= (n - 1) << __ffs(dd->div1_mask);
+ __raw_writel(v, dd->mult_div1_reg);
+
+ /* We let the clock framework set the other output dividers later */
+
+ /* REVISIT: Set ramp-up delay? */
+
+ _omap3_noncore_dpll_lock(clk);
+
+ return 0;
+}
+
+/* Public functions */
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+ return omap2_get_dpll_rate(clk);
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
/**
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
* @clk: pointer to a DPLL struct clk
@@ -292,48 +337,6 @@ void omap3_noncore_dpll_disable(struct clk *clk)
/* Non-CORE DPLL rate set code */
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock.. Returns -EINVAL upon error, or 0 upon success.
- */
-int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
- struct dpll_data *dd = clk->dpll_data;
- u32 v;
-
- /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
- _omap3_noncore_dpll_bypass(clk);
-
- /* Set jitter correction */
- if (!cpu_is_omap44xx()) {
- v = __raw_readl(dd->control_reg);
- v &= ~dd->freqsel_mask;
- v |= freqsel << __ffs(dd->freqsel_mask);
- __raw_writel(v, dd->control_reg);
- }
-
- /* Set DPLL multiplier, divider */
- v = __raw_readl(dd->mult_div1_reg);
- v &= ~(dd->mult_mask | dd->div1_mask);
- v |= m << __ffs(dd->mult_mask);
- v |= (n - 1) << __ffs(dd->div1_mask);
- __raw_writel(v, dd->mult_div1_reg);
-
- /* We let the clock framework set the other output dividers later */
-
- /* REVISIT: Set ramp-up delay? */
-
- _omap3_noncore_dpll_lock(clk);
-
- return 0;
-}
-
/**
* omap3_noncore_dpll_set_rate - set non-core DPLL rate
* @clk: struct clk * of DPLL to set
next prev parent reply other threads:[~2010-01-15 9:08 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-15 9:06 [PATCH 00/18] OMAP2/3/4 clock: split out code for clock types and clean up Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 01/18] OMAP3 clock: move OMAP3-specific DPLL functions to dpll3xxx.c Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 02/18] OMAP2/3/4 clock: move DPLL clock functions into clkt_dpll.c Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 03/18] OMAP2/3/4 clock: move clksel clock functions into clkt_clksel.c Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 04/18] OMAP2 clock: move all static functions to the top of the file Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 05/18] OMAP2/3/4 clock: combine all omap2_clk_functions Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 06/18] OMAP2xxx clock: move the DPLL+CORE composite clock code into clkt2xxx_dpllcore.c Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:06 ` [PATCH 07/18] OMAP2xxx clock: move the DVFS virtual clock code into clkt2xxx_virt_prcm_set.c Paul Walmsley
2010-01-15 9:06 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 08/18] OMAP2xxx clock: move the APLL clock code into clkt2xxx_apll.c Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 09/18] OMAP2xxx clock: move osc_clk code into clkt2xxx_osc.c Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 10/18] OMAP2xxx clock: move sys_clk code into clkt2xxx_sys.c Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 11/18] OMAP2 clock: don't compile OMAP2430-only functions on non-2430 builds Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 12/18] OMAP3 clock: split out DPLL3 M2 divider functions into clkt3xxx_dpll3m2.c Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 12:50 ` Alexander Shishkin
2010-01-19 18:36 ` Paul Walmsley
2010-01-19 18:36 ` Paul Walmsley
2010-01-20 13:56 ` Ranjith Lohithakshan
2010-01-20 13:56 ` Ranjith Lohithakshan
2010-01-15 9:07 ` [PATCH 13/18] OMAP2/3 clock: clean up omap*_clk_arch_init() Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 14/18] OMAP2/3 clock: remove unnecessary includes and clean up header Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 15/18] OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley [this message]
2010-01-15 9:07 ` [PATCH 16/18] OMAP3 DPLL: reorganize static functions Paul Walmsley
2010-01-15 9:07 ` [PATCH 17/18] OMAP clock: resolve all remaining sparse warnings Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
2010-01-15 9:07 ` [PATCH 18/18] OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions Paul Walmsley
2010-01-15 9:07 ` Paul Walmsley
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