diff for duplicates of <20100122203953.GA11835@atomide.com> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index e36ab16..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/x-diff; charset=us-ascii -Content-Disposition: inline; filename="multi-omap-entry-macro-v2.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 3186526..0000000 --- a/a/2.txt +++ /dev/null @@ -1,129 +0,0 @@ ->From 6f9a0d37612db2833d280748bedc9c35a2c366ab Mon Sep 17 00:00:00 2001 -From: Tony Lindgren <tony@atomide.com> -Date: Fri, 22 Jan 2010 11:36:16 -0800 -Subject: [PATCH] omap2/3: Make get_irqnr_and_base common for mach-omap2 multiboot - -Make get_irqnr_and_base common for mach-omap2 multiboot - -Note that this will only work currently for 24xx and 34xx. - -The overhead of this should be minimal, it basically adds one -cmp to see if omap_irq_base has been configured already. -If necessary, we can set separate optimized get_irqnr_and_base -for non-multiboot configurations. - -Support for 44xx can be added later on for basic multiboot, -and similar patch should be done for mach-omap1/entry-macro.S. - -Signed-off-by: Tony Lindgren <tony@atomide.com> - -diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S -index c7f1720..c5ea026 100644 ---- a/arch/arm/mach-omap2/include/mach/entry-macro.S -+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S -@@ -17,47 +17,85 @@ - - #include <plat/omap24xx.h> - #include <plat/omap34xx.h> -- --/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ --#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) --#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) --#elif defined(CONFIG_ARCH_OMAP34XX) --#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) --#endif --#if defined(CONFIG_ARCH_OMAP4) - #include <plat/omap44xx.h> --#endif --#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ --#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ - - .macro disable_fiq - .endm - -- .macro get_irqnr_preamble, base, tmp -- .endm -- - .macro arch_ret_to_user, tmp1, tmp2 - .endm - --#ifndef CONFIG_ARCH_OMAP4 -+#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) || \ -+ defined(CONFIG_ARCH_OMAP34XX) -+ -+#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) -+#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) -+#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ -+#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ -+ -+ .pushsection .data -+omap_irq_base: .word 0 -+ .popsection -+ -+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3) -+ /* Configure the interrupt base on the first interrupt */ -+ .macro get_irqnr_preamble, base, tmp -+9: -+ ldr \base, =omap_irq_base @ irq base address -+ ldr \base, [\base, #0] @ irq base value -+ cmp \base, #0 @ already configured? -+ bne 9998f @ nothing to do -+ -+ mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision -+ and \tmp, \tmp, #0x000f0000 @ only check architecture -+ cmp \tmp, #0x00060000 @ is v6? -+ beq 2400f @ found v6 so it's omap24xx -+ cmp \tmp, #0x000f0000 @ is cortex? -+ beq 3400f @ found v7 so it's omap34xx -+2400: ldr \base, =OMAP2_IRQ_BASE -+ ldr \tmp, =omap_irq_base -+ str \base, [\tmp, #0] -+ b 9b -+3400: ldr \base, =OMAP3_IRQ_BASE -+ ldr \tmp, =omap_irq_base -+ str \base, [\tmp, #0] -+ b 9b -+9998: -+ .endm -+#else -+ .macro get_irqnr_preamble, base, tmp -+#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) -+ ldr \base, =OMAP2_IRQ_BASE -+#else -+ ldr \base, =OMAP3_IRQ_BASE -+#endif -+ .endm -+#endif -+ /* Check the pending interrupts. Note that base already set */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -- ldr \base, =OMAP2_VA_IC_BASE - ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ - cmp \irqnr, #0x0 -- bne 2222f -+ bne 9999f - ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ - cmp \irqnr, #0x0 -- bne 2222f -+ bne 9999f - ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ - cmp \irqnr, #0x0 --2222: -+9999: - ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] - and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ - - .endm --#else -+#endif -+ -+ -+#ifdef CONFIG_ARCH_OMAP4 -+ - #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) - -+ .macro get_irqnr_preamble, base, tmp -+ .endm -+ - /* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: diff --git a/a/content_digest b/N1/content_digest index 0c347c4..8ca43f6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,11 @@ "ref\020100116013205.10065.95921.stgit@baageli.muru.com\0" "ref\020100116013520.10065.17921.stgit@baageli.muru.com\0" "ref\020100116115503.GA15904@n2100.arm.linux.org.uk\0" - "From\0Tony Lindgren <tony@atomide.com>\0" - "Subject\0Re: [PATCH 4/4] omap: Make get_irqnr_and_base common for mach-omap2 multiboot, v2\0" + "From\0tony@atomide.com (Tony Lindgren)\0" + "Subject\0[PATCH 4/4] omap: Make get_irqnr_and_base common for mach-omap2 multiboot, v2\0" "Date\0Fri, 22 Jan 2010 12:39:53 -0800\0" - "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - " linux-omap@vger.kernel.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "* Russell King - ARM Linux <linux@arm.linux.org.uk> [100116 03:53]:\n" "> On Fri, Jan 15, 2010 at 05:35:20PM -0800, Tony Lindgren wrote:\n" @@ -50,137 +48,5 @@ "Regards,\n" "\n" Tony - "\01:2\0" - "fn\0multi-omap-entry-macro-v2.patch\0" - "b\0" - ">From 6f9a0d37612db2833d280748bedc9c35a2c366ab Mon Sep 17 00:00:00 2001\n" - "From: Tony Lindgren <tony@atomide.com>\n" - "Date: Fri, 22 Jan 2010 11:36:16 -0800\n" - "Subject: [PATCH] omap2/3: Make get_irqnr_and_base common for mach-omap2 multiboot\n" - "\n" - "Make get_irqnr_and_base common for mach-omap2 multiboot\n" - "\n" - "Note that this will only work currently for 24xx and 34xx.\n" - "\n" - "The overhead of this should be minimal, it basically adds one\n" - "cmp to see if omap_irq_base has been configured already.\n" - "If necessary, we can set separate optimized get_irqnr_and_base\n" - "for non-multiboot configurations.\n" - "\n" - "Support for 44xx can be added later on for basic multiboot,\n" - "and similar patch should be done for mach-omap1/entry-macro.S.\n" - "\n" - "Signed-off-by: Tony Lindgren <tony@atomide.com>\n" - "\n" - "diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S\n" - "index c7f1720..c5ea026 100644\n" - "--- a/arch/arm/mach-omap2/include/mach/entry-macro.S\n" - "+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S\n" - "@@ -17,47 +17,85 @@\n" - " \n" - " #include <plat/omap24xx.h>\n" - " #include <plat/omap34xx.h>\n" - "-\n" - "-/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */\n" - "-#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)\n" - "-#define OMAP2_VA_IC_BASE\t\tOMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)\n" - "-#elif defined(CONFIG_ARCH_OMAP34XX)\n" - "-#define OMAP2_VA_IC_BASE\t\tOMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)\n" - "-#endif\n" - "-#if defined(CONFIG_ARCH_OMAP4)\n" - " #include <plat/omap44xx.h>\n" - "-#endif\n" - "-#define INTCPS_SIR_IRQ_OFFSET\t0x0040\t\t/* Active interrupt offset */\n" - "-#define\tACTIVEIRQ_MASK\t\t0x7f\t\t/* Active interrupt bits */\n" - " \n" - " \t\t.macro\tdisable_fiq\n" - " \t\t.endm\n" - " \n" - "-\t\t.macro get_irqnr_preamble, base, tmp\n" - "-\t\t.endm\n" - "-\n" - " \t\t.macro arch_ret_to_user, tmp1, tmp2\n" - " \t\t.endm\n" - " \n" - "-#ifndef CONFIG_ARCH_OMAP4\n" - "+#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) || \\\n" - "+\tdefined(CONFIG_ARCH_OMAP34XX)\n" - "+\n" - "+#define OMAP2_IRQ_BASE\t\tOMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)\n" - "+#define OMAP3_IRQ_BASE\t\tOMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)\n" - "+#define INTCPS_SIR_IRQ_OFFSET\t0x0040\t\t/* Active interrupt offset */\n" - "+#define\tACTIVEIRQ_MASK\t\t0x7f\t\t/* Active interrupt bits */\n" - "+\n" - "+\t\t.pushsection .data\n" - "+omap_irq_base:\t.word\t0\n" - "+\t\t.popsection\n" - "+\n" - "+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3)\n" - "+\t\t/* Configure the interrupt base on the first interrupt */\n" - "+\t\t.macro get_irqnr_preamble, base, tmp\n" - "+9:\n" - "+\t\tldr\t\\base, =omap_irq_base\t@ irq base address\n" - "+\t\tldr\t\\base, [\\base, #0]\t@ irq base value\n" - "+\t\tcmp\t\\base, #0\t\t@ already configured?\n" - "+\t\tbne\t9998f\t\t\t@ nothing to do\n" - "+\n" - "+\t\tmrc\tp15, 0, \\tmp, c0, c0, 0\t@ get processor revision\n" - "+\t\tand\t\\tmp, \\tmp, #0x000f0000\t@ only check architecture\n" - "+\t\tcmp\t\\tmp, #0x00060000\t@ is v6?\n" - "+\t\tbeq\t2400f\t\t\t@ found v6 so it's omap24xx\n" - "+\t\tcmp\t\\tmp, #0x000f0000\t@ is cortex?\n" - "+\t\tbeq\t3400f\t\t\t@ found v7 so it's omap34xx\n" - "+2400:\t\tldr\t\\base, =OMAP2_IRQ_BASE\n" - "+\t\tldr\t\\tmp, =omap_irq_base\n" - "+\t\tstr\t\\base, [\\tmp, #0]\n" - "+\t\tb\t9b\n" - "+3400:\t\tldr\t\\base, =OMAP3_IRQ_BASE\n" - "+\t\tldr\t\\tmp, =omap_irq_base\n" - "+\t\tstr\t\\base, [\\tmp, #0]\n" - "+\t\tb\t9b\n" - "+9998:\n" - "+\t\t.endm\n" - "+#else\n" - "+\t\t.macro get_irqnr_preamble, base, tmp\n" - "+#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)\n" - "+\t\tldr\t\\base, =OMAP2_IRQ_BASE\n" - "+#else\n" - "+\t\tldr\t\\base, =OMAP3_IRQ_BASE\n" - "+#endif\n" - "+\t\t.endm\n" - "+#endif\n" - "+\t\t/* Check the pending interrupts. Note that base already set */\n" - " \t\t.macro\tget_irqnr_and_base, irqnr, irqstat, base, tmp\n" - "-\t\tldr\t\\base, =OMAP2_VA_IC_BASE\n" - " \t\tldr\t\\irqnr, [\\base, #0x98] /* IRQ pending reg 1 */\n" - " \t\tcmp\t\\irqnr, #0x0\n" - "-\t\tbne\t2222f\n" - "+\t\tbne\t9999f\n" - " \t\tldr\t\\irqnr, [\\base, #0xb8] /* IRQ pending reg 2 */\n" - " \t\tcmp\t\\irqnr, #0x0\n" - "-\t\tbne\t2222f\n" - "+\t\tbne\t9999f\n" - " \t\tldr\t\\irqnr, [\\base, #0xd8] /* IRQ pending reg 3 */\n" - " \t\tcmp\t\\irqnr, #0x0\n" - "-2222:\n" - "+9999:\n" - " \t\tldrne\t\\irqnr, [\\base, #INTCPS_SIR_IRQ_OFFSET]\n" - " \t\tand\t\\irqnr, \\irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */\n" - " \n" - " \t\t.endm\n" - "-#else\n" - "+#endif\n" - "+\n" - "+\n" - "+#ifdef CONFIG_ARCH_OMAP4\n" - "+\n" - " #define OMAP44XX_VA_GIC_CPU_BASE\tOMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)\n" - " \n" - "+\t\t.macro get_irqnr_preamble, base, tmp\n" - "+\t\t.endm\n" - "+\n" - " \t\t/*\n" - " \t\t * The interrupt numbering scheme is defined in the\n" - " \t\t * interrupt controller spec. To wit:" -6404cafd2df9236a2ae0ecae59fd9acfd342bd190907fadc2c258f70c19aa3e1 +70db78c8f4ddc2e874399dd542e064ff141237a87a2355752d447084a1f49e06
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