[PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[Guenter Roeck]

Linux kernel 2.6.32 and later allocates memory from the top of virtual memory
space.

This patch implements virtual memory size detection for 64 bit MIPS CPUs
to avoid resulting crashes.

Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
---
 arch/mips/include/asm/cpu-features.h |    3 +++
 arch/mips/include/asm/cpu-info.h     |    1 +
 arch/mips/include/asm/pgtable-64.h   |    4 +++-
 arch/mips/kernel/cpu-probe.c         |   11 +++++++++++
 4 files changed, 18 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f4df64..284eb55 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -209,6 +209,9 @@
 # ifndef cpu_has_64bit_addresses
 # define cpu_has_64bit_addresses	1
 # endif
+# ifndef cpu_vmbits
+# define cpu_vmbits cpu_data[0].vmbits
+# endif
 #endif
 
 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 1260443..3c694bc 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -58,6 +58,7 @@ struct cpuinfo_mips {
 	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
 	int			srsets;	/* Shadow register sets */
 	int			core;	/* physical core number */
+	int			vmbits;	/* Virtual memory size in bits */
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 	/*
 	 * In the MIPS MT "SMTC" model, each TC is considered
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 9cd5089..259ec58 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -110,7 +110,9 @@
 #define VMALLOC_START		MAP_BASE
 #define VMALLOC_END	\
 	(VMALLOC_START + \
-	 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32))
+	 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
+	     (1UL<<cpu_vmbits)) - (1UL << 32))
+
 #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
 	VMALLOC_START != CKSSEG
 /* Load modules into 32bit-compatible segment. */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7a51866..909e378 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -282,6 +282,15 @@ static inline int __cpu_has_fpu(void)
 	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 }
 
+static inline void cpu_set_vmbits(struct cpuinfo_mips *c)
+{
+	if (cpu_has_64bits) {
+		write_c0_entryhi(0xfffffffffffff000ULL);
+		c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL);
+	} else
+		c->vmbits = 32;
+}
+
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 		| MIPS_CPU_COUNTER)
 
@@ -967,6 +976,8 @@ __cpuinit void cpu_probe(void)
 		c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 	else
 		c->srsets = 1;
+
+	cpu_set_vmbits(c);
 }
 
 __cpuinit void cpu_report(void)
-- 
1.6.0.4

Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[David Daney]

Guenter Roeck wrote:
> Linux kernel 2.6.32 and later allocates memory from the top of virtual memory
> space.
> 
> This patch implements virtual memory size detection for 64 bit MIPS CPUs
> to avoid resulting crashes.
> 
> Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
[...]
>  
> +static inline void cpu_set_vmbits(struct cpuinfo_mips *c)
> +{
> +	if (cpu_has_64bits) {
> +		write_c0_entryhi(0xfffffffffffff000ULL);

macro indicated that we need to avoid hazards here on R4000.

Perhaps adding:

  	back_to_back_c0_hazard();

> +		c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL);
> +	} else
> +		c->vmbits = 32;
> +}
> +

Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[Guenter Roeck]

On Mon, Feb 01, 2010 at 06:44:21PM -0500, David Daney wrote:
> Guenter Roeck wrote:
> > Linux kernel 2.6.32 and later allocates memory from the top of virtual memory
> > space.
> > 
> > This patch implements virtual memory size detection for 64 bit MIPS CPUs
> > to avoid resulting crashes.
> > 
> > Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
> [...]
> >  
> > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c)
> > +{
> > +	if (cpu_has_64bits) {
> > +		write_c0_entryhi(0xfffffffffffff000ULL);
> 
> macro indicated that we need to avoid hazards here on R4000.
> 
> Perhaps adding:
> 
>   	back_to_back_c0_hazard();
> 
Compiler already added a nop, so I thought it wasn't necessary.
Doesn't hurt either, so I'll put it in.

Guenter

Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[Ralf Baechle]

On Mon, Feb 01, 2010 at 04:10:26PM -0800, Guenter Roeck wrote:

> > > +	if (cpu_has_64bits) {
> > > +		write_c0_entryhi(0xfffffffffffff000ULL);
> > 
> > macro indicated that we need to avoid hazards here on R4000.

A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but
will read from the same register on stage 4 which leaves a window of
2 instructions, that is 2 NOP instructions needed.

> > Perhaps adding:
> > 
> >   	back_to_back_c0_hazard();
> > 
> Compiler already added a nop, so I thought it wasn't necessary.
> Doesn't hurt either, so I'll put it in.

This probe is needed as per MIPSxx architecture spec and several CPUs will
missbehave without it.  The 74K which of course is 32-bit but it
illustrates the issue might even issue these instructions out of order.
back_to_back_c0_hazard will expand into a suitable sequence to handle
the pipeline hazard.  And we can't trust on the compiler doing the right
thing here; as explained above we might need multiple nops and some CPUs
will need other instructions to deal with the hazard, for example a number
of SSNOPs or an EHB instruction.

  Ralf

Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

[Maciej W. Rozycki]

On Tue, 2 Feb 2010, Ralf Baechle wrote:

> > > > +	if (cpu_has_64bits) {
> > > > +		write_c0_entryhi(0xfffffffffffff000ULL);
> > > 
> > > macro indicated that we need to avoid hazards here on R4000.
> 
> A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but
> will read from the same register on stage 4 which leaves a window of
> 2 instructions, that is 2 NOP instructions needed.

 A footnote says: "An MTC0 of a CPR must not be immediately followed by 
MFC0 of the same CPR." -- that seems to imply a single intermediate 
instruction is sufficient, but that's not stated explicitly and obviously 
adding an extraneous instruction here, where performance does not matter, 
cannot hurt.

> > > Perhaps adding:
> > > 
> > >   	back_to_back_c0_hazard();
> > > 
> > Compiler already added a nop, so I thought it wasn't necessary.
> > Doesn't hurt either, so I'll put it in.
> 
> This probe is needed as per MIPSxx architecture spec and several CPUs will
> missbehave without it.  The 74K which of course is 32-bit but it
> illustrates the issue might even issue these instructions out of order.
> back_to_back_c0_hazard will expand into a suitable sequence to handle
> the pipeline hazard.  And we can't trust on the compiler doing the right
> thing here; as explained above we might need multiple nops and some CPUs
> will need other instructions to deal with the hazard, for example a number
> of SSNOPs or an EHB instruction.

 I reckon there are MIPS64r2 ISA implementations out there already, so an 
EHB is a necessity where appropriate.

  Maciej