diff for duplicates of <20100203132404.GC5252@k2> diff --git a/a/1.txt b/N1/1.txt index 42a8bec..839f84c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -10,23 +10,23 @@ On 10 Feb 02, Eric Miao wrote: > > > > Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> > > --- -> > ?arch/arm/plat-mxc/Kconfig ?| ? ?8 ++ -> > ?arch/arm/plat-mxc/Makefile | ? ?3 + -> > ?arch/arm/plat-mxc/tzic.c ? | ?182 ++++++++++++++++++++++++++++++++++++++++++++ -> > ?3 files changed, 193 insertions(+), 0 deletions(-) -> > ?create mode 100644 arch/arm/plat-mxc/tzic.c +> > arch/arm/plat-mxc/Kconfig | 8 ++ +> > arch/arm/plat-mxc/Makefile | 3 + +> > arch/arm/plat-mxc/tzic.c | 182 ++++++++++++++++++++++++++++++++++++++++++++ +> > 3 files changed, 193 insertions(+), 0 deletions(-) +> > create mode 100644 arch/arm/plat-mxc/tzic.c > > > > diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig > > index 8b0a1ee..59558c4 100644 > > --- a/arch/arm/plat-mxc/Kconfig > > +++ b/arch/arm/plat-mxc/Kconfig > > @@ -62,6 +62,14 @@ config MXC_IRQ_PRIOR -> > ? ? ? ? ?requirements for timing. -> > ? ? ? ? ?Say N here, unless you have a specialized requirement. +> > requirements for timing. +> > Say N here, unless you have a specialized requirement. > > > > +config MXC_TZIC -> > + ? ? ? bool "Enable TrustZone Interrupt Controller" -> > + ? ? ? depends on ARCH_MX51 +> > + bool "Enable TrustZone Interrupt Controller" +> > + depends on ARCH_MX51 > > This is the first patch of the base port, yet I cannot find any reference to > this ARCH_MX51, did you miss something? @@ -37,28 +37,28 @@ processor to use it), I thought of splitting it out as a separate patch. Does this break the sanctity of one self-contained change? -> > + ? ? ? help -> > + ? ? ? ? This will be automatically selected for all processors -> > + ? ? ? ? containing this interrupt controller. -> > + ? ? ? ? Say N here only if you are really sure. +> > + help +> > + This will be automatically selected for all processors +> > + containing this interrupt controller. +> > + Say N here only if you are really sure. > > + -> > ?config MXC_PWM -> > ? ? ? ?tristate "Enable PWM driver" -> > ? ? ? ?depends on ARCH_MXC +> > config MXC_PWM +> > tristate "Enable PWM driver" +> > depends on ARCH_MXC > > diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile > > index 996cbac..0202ad9 100644 > > --- a/arch/arm/plat-mxc/Makefile > > +++ b/arch/arm/plat-mxc/Makefile > > @@ -5,6 +5,9 @@ -> > ?# Common support -> > ?obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +> > # Common support +> > obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o > > > > +# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) > > +obj-$(CONFIG_MXC_TZIC) += tzic.o > > + -> > ?obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o -> > ?obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o -> > ?obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o +> > obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o +> > obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o +> > obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o > > diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c > > new file mode 100644 > > index 0000000..00cb0ad @@ -89,27 +89,27 @@ Does this break the sanctity of one self-contained change? > > + > > +/* > > + ***************************************** -> > + * TZIC Registers ? ? ? ? ? ? ? ? ? ? ? ?* +> > + * TZIC Registers * > > + ***************************************** > > + */ > > + -> > +#define TZIC_INTCNTL ? ? ? ? ? ?0x0000 /* Control register */ -> > +#define TZIC_INTTYPE ? ? ? ? ? ?0x0004 /* Controller Type register */ -> > +#define TZIC_IMPID ? ? ? ? ? ? ?0x0008 /* Distributor Implementer Identification */ -> > +#define TZIC_PRIOMASK ? ? ? ? ? 0x000C /* Priority Mask Reg */ -> > +#define TZIC_SYNCCTRL ? ? ? ? ? 0x0010 /* Synchronizer Control register */ -> > +#define TZIC_DSMINT ? ? ? ? ? ? 0x0014 /* DSM interrupt Holdoffregister */ -> > +#define TZIC_INTSEC0 ? ? ? ? ? ?0x0080 /* Interrupt Security register 0 */ -> > +#define TZIC_ENSET0 ? ? ? ? ? ? 0x0100 /* Enable Set Register 0 */ -> > +#define TZIC_ENCLEAR0 ? ? ? ? ? 0x0180 /* Enable Clear Register 0 */ -> > +#define TZIC_SRCSET0 ? ? ? ? ? ?0x0200 /* Source Set Register 0 */ -> > +#define TZIC_SRCCLAR0 ? ? ? ? ? 0x0280 /* Source Clear Register 0 */ -> > +#define TZIC_PRIORITY0 ? ? ? ? ?0x0400 /* Priority Register 0 */ -> > +#define TZIC_PND0 ? ? ? ? ? ? ? 0x0D00 /* Pending Register 0 */ -> > +#define TZIC_HIPND0 ? ? ? ? ? ? 0x0D80 /* High Priority Pending Register */ -> > +#define TZIC_WAKEUP0 ? ? ? ? ? ?0x0E00 /* Wakeup Config Register */ -> > +#define TZIC_SWINT ? ? ? ? ? ? ?0x0F00 /* Software Interrupt Rigger Register */ -> > +#define TZIC_ID0 ? ? ? ? ? ? ? ?0x0FD0 /* Indentification Register 0 */ +> > +#define TZIC_INTCNTL 0x0000 /* Control register */ +> > +#define TZIC_INTTYPE 0x0004 /* Controller Type register */ +> > +#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ +> > +#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ +> > +#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ +> > +#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ +> > +#define TZIC_INTSEC0 0x0080 /* Interrupt Security register 0 */ +> > +#define TZIC_ENSET0 0x0100 /* Enable Set Register 0 */ +> > +#define TZIC_ENCLEAR0 0x0180 /* Enable Clear Register 0 */ +> > +#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ +> > +#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ +> > +#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ +> > +#define TZIC_PND0 0x0D00 /* Pending Register 0 */ +> > +#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ +> > +#define TZIC_WAKEUP0 0x0E00 /* Wakeup Config Register */ +> > +#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ +> > +#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ > > + > > +void __iomem *tzic_base; > @@ -133,15 +133,15 @@ AVIC's way of doing things. OK. > > + * -> > + * @param ?irq ? ? ? ? ?interrupt source number +> > + * @param irq interrupt source number > > + */ > > +static void tzic_mask_irq(unsigned int irq) > > +{ -> > + ? ? ? int index, off; +> > + int index, off; > > + -> > + ? ? ? index = irq >> 5; -> > + ? ? ? off = irq & 0x1F; -> > + ? ? ? __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0 + (index << 2)); +> > + index = irq >> 5; +> > + off = irq & 0x1F; +> > + __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0 + (index << 2)); > > I'll normally define TZIC_ENCLEAR0 then as: > @@ -162,15 +162,15 @@ OK. > > +/* > > + * Enable interrupt number "irq" in the TZIC > > + * -> > + * @param ?irq ? ? ? ? ?interrupt source number +> > + * @param irq interrupt source number > > + */ > > +static void tzic_unmask_irq(unsigned int irq) > > +{ -> > + ? ? ? int index, off; +> > + int index, off; > > + -> > + ? ? ? index = irq >> 5; -> > + ? ? ? off = irq & 0x1F; -> > + ? ? ? __raw_writel(1 << off, tzic_base + TZIC_ENSET0 + (index << 2)); +> > + index = irq >> 5; +> > + off = irq & 0x1F; +> > + __raw_writel(1 << off, tzic_base + TZIC_ENSET0 + (index << 2)); > > +} > > + > > +static unsigned int wakeup_intr[4]; @@ -178,36 +178,36 @@ OK. > > +/* > > + * Set interrupt number "irq" in the TZIC as a wake-up source. > > + * -> > + * @param ?irq ? ? ? ? ?interrupt source number -> > + * @param ?enable ? ? ? enable as wake-up if equal to non-zero -> > + * ? ? ? ? ? ? ? ? ? ? disble as wake-up if equal to zero +> > + * @param irq interrupt source number +> > + * @param enable enable as wake-up if equal to non-zero +> > + * disble as wake-up if equal to zero > > + * -> > + * @return ? ? ? This function returns 0 on success. +> > + * @return This function returns 0 on success. > > + */ > > +static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) > > +{ -> > + ? ? ? unsigned int index, off; +> > + unsigned int index, off; > > + -> > + ? ? ? index = irq >> 5; -> > + ? ? ? off = irq & 0x1F; +> > + index = irq >> 5; +> > + off = irq & 0x1F; > > + -> > + ? ? ? if (index > 3) -> > + ? ? ? ? ? ? ? return -EINVAL; +> > + if (index > 3) +> > + return -EINVAL; > > + -> > + ? ? ? if (enable) -> > + ? ? ? ? ? ? ? wakeup_intr[index] |= (1 << off); -> > + ? ? ? else -> > + ? ? ? ? ? ? ? wakeup_intr[index] &= ~(1 << off); +> > + if (enable) +> > + wakeup_intr[index] |= (1 << off); +> > + else +> > + wakeup_intr[index] &= ~(1 << off); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static struct irq_chip mxc_tzic_chip = { -> > + ? ? ? .name = "MXC_TZIC", -> > + ? ? ? .ack = tzic_mask_irq, -> > + ? ? ? .mask = tzic_mask_irq, -> > + ? ? ? .unmask = tzic_unmask_irq, -> > + ? ? ? .set_wake = tzic_set_wake_irq, +> > + .name = "MXC_TZIC", +> > + .ack = tzic_mask_irq, +> > + .mask = tzic_mask_irq, +> > + .unmask = tzic_unmask_irq, +> > + .set_wake = tzic_set_wake_irq, > > +}; > > + > > +/* @@ -217,13 +217,13 @@ OK. > > + */ > > +void __init tzic_init_irq(void __iomem *irqbase) > > +{ -> > + ? ? ? int i; +> > + int i; > > + -> > + ? ? ? tzic_base = irqbase; -> > + ? ? ? /* put the TZIC into the reset value with -> > + ? ? ? ?* all interrupts disabled -> > + ? ? ? ?*/ -> > + ? ? ? i = __raw_readl(tzic_base + TZIC_INTCNTL); +> > + tzic_base = irqbase; +> > + /* put the TZIC into the reset value with +> > + * all interrupts disabled +> > + */ +> > + i = __raw_readl(tzic_base + TZIC_INTCNTL); > > Mixing the use of 'i' as both a signed counter and register value might > not be a good idea, provided it's not guaranteed from theory that 'i' as @@ -233,12 +233,12 @@ OK. Fair enough. > > + -> > + ? ? ? __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); -> > + ? ? ? i = __raw_readl(tzic_base + TZIC_INTCNTL); -> > + ? ? ? __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); -> > + ? ? ? i = __raw_readl(tzic_base + TZIC_PRIOMASK); -> > + ? ? ? __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); -> > + ? ? ? i = __raw_readl(tzic_base + TZIC_SYNCCTRL); +> > + __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); +> > + i = __raw_readl(tzic_base + TZIC_INTCNTL); +> > + __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); +> > + i = __raw_readl(tzic_base + TZIC_PRIOMASK); +> > + __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); +> > + i = __raw_readl(tzic_base + TZIC_SYNCCTRL); > > Are these read-back really necessary? We can start without them and add them > later if they do cause issues. @@ -248,22 +248,22 @@ Can anybody from Freescale comment whether the read-back is necessary? I'll remove it for now to see what happens in my testing. > > + -> > + ? ? ? for (i = 0; i < 4; i++) -> > + ? ? ? ? ? ? ? __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0 + i * 4); +> > + for (i = 0; i < 4; i++) +> > + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0 + i * 4); > > + -> > + ? ? ? /* disable all interrupts */ -> > + ? ? ? for (i = 0; i < 4; i++) -> > + ? ? ? ? ? ? ? __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0 + i * 4); +> > + /* disable all interrupts */ +> > + for (i = 0; i < 4; i++) +> > + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0 + i * 4); > > + -> > + ? ? ? /* all IRQ no FIQ Warning :: No selection */ +> > + /* all IRQ no FIQ Warning :: No selection */ > > + -> > + ? ? ? for (i = 0; i < MXC_INTERNAL_IRQS; i++) { -> > + ? ? ? ? ? ? ? set_irq_chip(i, &mxc_tzic_chip); -> > + ? ? ? ? ? ? ? set_irq_handler(i, handle_level_irq); -> > + ? ? ? ? ? ? ? set_irq_flags(i, IRQF_VALID); -> > + ? ? ? } +> > + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { +> > + set_irq_chip(i, &mxc_tzic_chip); +> > + set_irq_handler(i, handle_level_irq); +> > + set_irq_flags(i, IRQF_VALID); +> > + } > > + -> > + ? ? ? printk(KERN_INFO "TrustZone Interrupt Controller (TZIC) initialized\n"); +> > + printk(KERN_INFO "TrustZone Interrupt Controller (TZIC) initialized\n"); > > You may want to use pr_info() for short. @@ -274,35 +274,35 @@ OK > > +/* > > + * enable wakeup interrupt > > + * -> > + * @param is_idle ? ? ? ? ? ? ?1 if called in idle loop (ENSET register); -> > + * ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 to be used when called from low power entry -> > + * @return ? ? ? ? ? ? ? ? ? ? 0 if successful; non-zero otherwise +> > + * @param is_idle 1 if called in idle loop (ENSET register); +> > + * 0 to be used when called from low power entry +> > + * @return 0 if successful; non-zero otherwise > > + * > > + */ > > +int tzic_enable_wake(int is_idle) > > +{ -> > + ? ? ? unsigned int i, v; +> > + unsigned int i, v; > > + -> > + ? ? ? __raw_writel(1, tzic_base + TZIC_DSMINT); -> > + ? ? ? if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) -> > + ? ? ? ? ? ? ? return -EAGAIN; +> > + __raw_writel(1, tzic_base + TZIC_DSMINT); +> > + if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) +> > + return -EAGAIN; > > Looks like an unnecessary read-back provided the silicon is sane enough. Again, Dinh/Rob can you comment? > > + -> > + ? ? ? if (likely(is_idle)) { -> > + ? ? ? ? ? ? ? for (i = 0; i < 4; i++) { -> > + ? ? ? ? ? ? ? ? ? ? ? v = __raw_readl(tzic_base + TZIC_ENSET0 + i * 4); -> > + ? ? ? ? ? ? ? ? ? ? ? __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4); -> > + ? ? ? ? ? ? ? } -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? for (i = 0; i < 4; i++) { -> > + ? ? ? ? ? ? ? ? ? ? ? v = wakeup_intr[i]; -> > + ? ? ? ? ? ? ? ? ? ? ? __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4); -> > + ? ? ? ? ? ? ? } -> > + ? ? ? } +> > + if (likely(is_idle)) { +> > + for (i = 0; i < 4; i++) { +> > + v = __raw_readl(tzic_base + TZIC_ENSET0 + i * 4); +> > + __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4); +> > + } +> > + } else { +> > + for (i = 0; i < 4; i++) { +> > + v = wakeup_intr[i]; +> > + __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4); +> > + } +> > + } > > Or could be simplified to: > @@ -315,7 +315,7 @@ OK > but just nit-picking comments, so it's up to you. > -> > + ? ? ? return 0; +> > + return 0; > > +} > > Mmmm.... this being called elsewhere, I'm thinking about making this a @@ -329,5 +329,5 @@ Thanks for the review. /Amit -- ---------------------------------------------------------------------- -Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com +Amit Kucheria, Kernel Engineer || amit.kucheria@canonical.com ---------------------------------------------------------------------- diff --git a/a/content_digest b/N1/content_digest index 1a10677..40b3e03 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,20 @@ "ref\0cover.1265173246.git.amit.kucheria@verdurent.com\0" "ref\00511204199ab83aed2340e70a4639500c0528dab.1265173480.git.amit.kucheria@canonical.com\0" "ref\0f17812d71002022223jdc0ac5cp5b94928fb45695d6@mail.gmail.com\0" - "From\0amit.kucheria@canonical.com (Amit Kucheria)\0" - "Subject\0[PATCHv2 01/11] arm: mxc: TrustZone interrupt controller (TZIC) for i.MX5 family\0" + "From\0Amit Kucheria <amit.kucheria@canonical.com>\0" + "Subject\0Re: [PATCHv2 01/11] arm: mxc: TrustZone interrupt controller (TZIC) for i.MX5 family\0" "Date\0Wed, 3 Feb 2010 05:24:04 -0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Eric Miao <eric.y.miao@gmail.com>\0" + "Cc\0List Linux Kernel <linux-kernel@vger.kernel.org>" + linux@arm.linux.org.uk + Dinh.Nguyen@freescale.com + s.hauer@pengutronix.de + grant.likely@secretlab.ca + r.herring@freescale.com + linux-arm-kernel@lists.infradead.org + daniel@caiaq.de + bryan.wu@canonical.com + " valentin.longchamp@epfl.ch\0" "\00:1\0" "b\0" "On 10 Feb 02, Eric Miao wrote:\n" @@ -20,23 +30,23 @@ "> >\n" "> > Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>\n" "> > ---\n" - "> > ?arch/arm/plat-mxc/Kconfig ?| ? ?8 ++\n" - "> > ?arch/arm/plat-mxc/Makefile | ? ?3 +\n" - "> > ?arch/arm/plat-mxc/tzic.c ? | ?182 ++++++++++++++++++++++++++++++++++++++++++++\n" - "> > ?3 files changed, 193 insertions(+), 0 deletions(-)\n" - "> > ?create mode 100644 arch/arm/plat-mxc/tzic.c\n" + "> > \302\240arch/arm/plat-mxc/Kconfig \302\240| \302\240 \302\2408 ++\n" + "> > \302\240arch/arm/plat-mxc/Makefile | \302\240 \302\2403 +\n" + "> > \302\240arch/arm/plat-mxc/tzic.c \302\240 | \302\240182 ++++++++++++++++++++++++++++++++++++++++++++\n" + "> > \302\2403 files changed, 193 insertions(+), 0 deletions(-)\n" + "> > \302\240create mode 100644 arch/arm/plat-mxc/tzic.c\n" "> >\n" "> > diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig\n" "> > index 8b0a1ee..59558c4 100644\n" "> > --- a/arch/arm/plat-mxc/Kconfig\n" "> > +++ b/arch/arm/plat-mxc/Kconfig\n" "> > @@ -62,6 +62,14 @@ config MXC_IRQ_PRIOR\n" - "> > ? ? ? ? ?requirements for timing.\n" - "> > ? ? ? ? ?Say N here, unless you have a specialized requirement.\n" + "> > \302\240 \302\240 \302\240 \302\240 \302\240requirements for timing.\n" + "> > \302\240 \302\240 \302\240 \302\240 \302\240Say N here, unless you have a specialized requirement.\n" "> >\n" "> > +config MXC_TZIC\n" - "> > + ? ? ? bool \"Enable TrustZone Interrupt Controller\"\n" - "> > + ? ? ? depends on ARCH_MX51\n" + "> > + \302\240 \302\240 \302\240 bool \"Enable TrustZone Interrupt Controller\"\n" + "> > + \302\240 \302\240 \302\240 depends on ARCH_MX51\n" "> \n" "> This is the first patch of the base port, yet I cannot find any reference to\n" "> this ARCH_MX51, did you miss something?\n" @@ -47,28 +57,28 @@ "\n" "Does this break the sanctity of one self-contained change?\n" "\n" - "> > + ? ? ? help\n" - "> > + ? ? ? ? This will be automatically selected for all processors\n" - "> > + ? ? ? ? containing this interrupt controller.\n" - "> > + ? ? ? ? Say N here only if you are really sure.\n" + "> > + \302\240 \302\240 \302\240 help\n" + "> > + \302\240 \302\240 \302\240 \302\240 This will be automatically selected for all processors\n" + "> > + \302\240 \302\240 \302\240 \302\240 containing this interrupt controller.\n" + "> > + \302\240 \302\240 \302\240 \302\240 Say N here only if you are really sure.\n" "> > +\n" - "> > ?config MXC_PWM\n" - "> > ? ? ? ?tristate \"Enable PWM driver\"\n" - "> > ? ? ? ?depends on ARCH_MXC\n" + "> > \302\240config MXC_PWM\n" + "> > \302\240 \302\240 \302\240 \302\240tristate \"Enable PWM driver\"\n" + "> > \302\240 \302\240 \302\240 \302\240depends on ARCH_MXC\n" "> > diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile\n" "> > index 996cbac..0202ad9 100644\n" "> > --- a/arch/arm/plat-mxc/Makefile\n" "> > +++ b/arch/arm/plat-mxc/Makefile\n" "> > @@ -5,6 +5,9 @@\n" - "> > ?# Common support\n" - "> > ?obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o\n" + "> > \302\240# Common support\n" + "> > \302\240obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o\n" "> >\n" "> > +# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)\n" "> > +obj-$(CONFIG_MXC_TZIC) += tzic.o\n" "> > +\n" - "> > ?obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o\n" - "> > ?obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o\n" - "> > ?obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o\n" + "> > \302\240obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o\n" + "> > \302\240obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o\n" + "> > \302\240obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o\n" "> > diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c\n" "> > new file mode 100644\n" "> > index 0000000..00cb0ad\n" @@ -99,27 +109,27 @@ "> > +\n" "> > +/*\n" "> > + *****************************************\n" - "> > + * TZIC Registers ? ? ? ? ? ? ? ? ? ? ? ?*\n" + "> > + * TZIC Registers \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240*\n" "> > + *****************************************\n" "> > + */\n" "> > +\n" - "> > +#define TZIC_INTCNTL ? ? ? ? ? ?0x0000 /* Control register */\n" - "> > +#define TZIC_INTTYPE ? ? ? ? ? ?0x0004 /* Controller Type register */\n" - "> > +#define TZIC_IMPID ? ? ? ? ? ? ?0x0008 /* Distributor Implementer Identification */\n" - "> > +#define TZIC_PRIOMASK ? ? ? ? ? 0x000C /* Priority Mask Reg */\n" - "> > +#define TZIC_SYNCCTRL ? ? ? ? ? 0x0010 /* Synchronizer Control register */\n" - "> > +#define TZIC_DSMINT ? ? ? ? ? ? 0x0014 /* DSM interrupt Holdoffregister */\n" - "> > +#define TZIC_INTSEC0 ? ? ? ? ? ?0x0080 /* Interrupt Security register 0 */\n" - "> > +#define TZIC_ENSET0 ? ? ? ? ? ? 0x0100 /* Enable Set Register 0 */\n" - "> > +#define TZIC_ENCLEAR0 ? ? ? ? ? 0x0180 /* Enable Clear Register 0 */\n" - "> > +#define TZIC_SRCSET0 ? ? ? ? ? ?0x0200 /* Source Set Register 0 */\n" - "> > +#define TZIC_SRCCLAR0 ? ? ? ? ? 0x0280 /* Source Clear Register 0 */\n" - "> > +#define TZIC_PRIORITY0 ? ? ? ? ?0x0400 /* Priority Register 0 */\n" - "> > +#define TZIC_PND0 ? ? ? ? ? ? ? 0x0D00 /* Pending Register 0 */\n" - "> > +#define TZIC_HIPND0 ? ? ? ? ? ? 0x0D80 /* High Priority Pending Register */\n" - "> > +#define TZIC_WAKEUP0 ? ? ? ? ? ?0x0E00 /* Wakeup Config Register */\n" - "> > +#define TZIC_SWINT ? ? ? ? ? ? ?0x0F00 /* Software Interrupt Rigger Register */\n" - "> > +#define TZIC_ID0 ? ? ? ? ? ? ? ?0x0FD0 /* Indentification Register 0 */\n" + "> > +#define TZIC_INTCNTL \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0000 /* Control register */\n" + "> > +#define TZIC_INTTYPE \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0004 /* Controller Type register */\n" + "> > +#define TZIC_IMPID \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0008 /* Distributor Implementer Identification */\n" + "> > +#define TZIC_PRIOMASK \302\240 \302\240 \302\240 \302\240 \302\240 0x000C /* Priority Mask Reg */\n" + "> > +#define TZIC_SYNCCTRL \302\240 \302\240 \302\240 \302\240 \302\240 0x0010 /* Synchronizer Control register */\n" + "> > +#define TZIC_DSMINT \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x0014 /* DSM interrupt Holdoffregister */\n" + "> > +#define TZIC_INTSEC0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0080 /* Interrupt Security register 0 */\n" + "> > +#define TZIC_ENSET0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x0100 /* Enable Set Register 0 */\n" + "> > +#define TZIC_ENCLEAR0 \302\240 \302\240 \302\240 \302\240 \302\240 0x0180 /* Enable Clear Register 0 */\n" + "> > +#define TZIC_SRCSET0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0200 /* Source Set Register 0 */\n" + "> > +#define TZIC_SRCCLAR0 \302\240 \302\240 \302\240 \302\240 \302\240 0x0280 /* Source Clear Register 0 */\n" + "> > +#define TZIC_PRIORITY0 \302\240 \302\240 \302\240 \302\240 \302\2400x0400 /* Priority Register 0 */\n" + "> > +#define TZIC_PND0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x0D00 /* Pending Register 0 */\n" + "> > +#define TZIC_HIPND0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x0D80 /* High Priority Pending Register */\n" + "> > +#define TZIC_WAKEUP0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0E00 /* Wakeup Config Register */\n" + "> > +#define TZIC_SWINT \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0F00 /* Software Interrupt Rigger Register */\n" + "> > +#define TZIC_ID0 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x0FD0 /* Indentification Register 0 */\n" "> > +\n" "> > +void __iomem *tzic_base;\n" "> \n" @@ -143,15 +153,15 @@ "OK.\n" "\n" "> > + *\n" - "> > + * @param ?irq ? ? ? ? ?interrupt source number\n" + "> > + * @param \302\240irq \302\240 \302\240 \302\240 \302\240 \302\240interrupt source number\n" "> > + */\n" "> > +static void tzic_mask_irq(unsigned int irq)\n" "> > +{\n" - "> > + ? ? ? int index, off;\n" + "> > + \302\240 \302\240 \302\240 int index, off;\n" "> > +\n" - "> > + ? ? ? index = irq >> 5;\n" - "> > + ? ? ? off = irq & 0x1F;\n" - "> > + ? ? ? __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0 + (index << 2));\n" + "> > + \302\240 \302\240 \302\240 index = irq >> 5;\n" + "> > + \302\240 \302\240 \302\240 off = irq & 0x1F;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0 + (index << 2));\n" "> \n" "> I'll normally define TZIC_ENCLEAR0 then as:\n" "> \n" @@ -172,15 +182,15 @@ "> > +/*\n" "> > + * Enable interrupt number \"irq\" in the TZIC\n" "> > + *\n" - "> > + * @param ?irq ? ? ? ? ?interrupt source number\n" + "> > + * @param \302\240irq \302\240 \302\240 \302\240 \302\240 \302\240interrupt source number\n" "> > + */\n" "> > +static void tzic_unmask_irq(unsigned int irq)\n" "> > +{\n" - "> > + ? ? ? int index, off;\n" + "> > + \302\240 \302\240 \302\240 int index, off;\n" "> > +\n" - "> > + ? ? ? index = irq >> 5;\n" - "> > + ? ? ? off = irq & 0x1F;\n" - "> > + ? ? ? __raw_writel(1 << off, tzic_base + TZIC_ENSET0 + (index << 2));\n" + "> > + \302\240 \302\240 \302\240 index = irq >> 5;\n" + "> > + \302\240 \302\240 \302\240 off = irq & 0x1F;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(1 << off, tzic_base + TZIC_ENSET0 + (index << 2));\n" "> > +}\n" "> > +\n" "> > +static unsigned int wakeup_intr[4];\n" @@ -188,36 +198,36 @@ "> > +/*\n" "> > + * Set interrupt number \"irq\" in the TZIC as a wake-up source.\n" "> > + *\n" - "> > + * @param ?irq ? ? ? ? ?interrupt source number\n" - "> > + * @param ?enable ? ? ? enable as wake-up if equal to non-zero\n" - "> > + * ? ? ? ? ? ? ? ? ? ? disble as wake-up if equal to zero\n" + "> > + * @param \302\240irq \302\240 \302\240 \302\240 \302\240 \302\240interrupt source number\n" + "> > + * @param \302\240enable \302\240 \302\240 \302\240 enable as wake-up if equal to non-zero\n" + "> > + * \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 disble as wake-up if equal to zero\n" "> > + *\n" - "> > + * @return ? ? ? This function returns 0 on success.\n" + "> > + * @return \302\240 \302\240 \302\240 This function returns 0 on success.\n" "> > + */\n" "> > +static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)\n" "> > +{\n" - "> > + ? ? ? unsigned int index, off;\n" + "> > + \302\240 \302\240 \302\240 unsigned int index, off;\n" "> > +\n" - "> > + ? ? ? index = irq >> 5;\n" - "> > + ? ? ? off = irq & 0x1F;\n" + "> > + \302\240 \302\240 \302\240 index = irq >> 5;\n" + "> > + \302\240 \302\240 \302\240 off = irq & 0x1F;\n" "> > +\n" - "> > + ? ? ? if (index > 3)\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (index > 3)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" "> > +\n" - "> > + ? ? ? if (enable)\n" - "> > + ? ? ? ? ? ? ? wakeup_intr[index] |= (1 << off);\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? wakeup_intr[index] &= ~(1 << off);\n" + "> > + \302\240 \302\240 \302\240 if (enable)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 wakeup_intr[index] |= (1 << off);\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 wakeup_intr[index] &= ~(1 << off);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static struct irq_chip mxc_tzic_chip = {\n" - "> > + ? ? ? .name = \"MXC_TZIC\",\n" - "> > + ? ? ? .ack = tzic_mask_irq,\n" - "> > + ? ? ? .mask = tzic_mask_irq,\n" - "> > + ? ? ? .unmask = tzic_unmask_irq,\n" - "> > + ? ? ? .set_wake = tzic_set_wake_irq,\n" + "> > + \302\240 \302\240 \302\240 .name = \"MXC_TZIC\",\n" + "> > + \302\240 \302\240 \302\240 .ack = tzic_mask_irq,\n" + "> > + \302\240 \302\240 \302\240 .mask = tzic_mask_irq,\n" + "> > + \302\240 \302\240 \302\240 .unmask = tzic_unmask_irq,\n" + "> > + \302\240 \302\240 \302\240 .set_wake = tzic_set_wake_irq,\n" "> > +};\n" "> > +\n" "> > +/*\n" @@ -227,13 +237,13 @@ "> > + */\n" "> > +void __init tzic_init_irq(void __iomem *irqbase)\n" "> > +{\n" - "> > + ? ? ? int i;\n" + "> > + \302\240 \302\240 \302\240 int i;\n" "> > +\n" - "> > + ? ? ? tzic_base = irqbase;\n" - "> > + ? ? ? /* put the TZIC into the reset value with\n" - "> > + ? ? ? ?* all interrupts disabled\n" - "> > + ? ? ? ?*/\n" - "> > + ? ? ? i = __raw_readl(tzic_base + TZIC_INTCNTL);\n" + "> > + \302\240 \302\240 \302\240 tzic_base = irqbase;\n" + "> > + \302\240 \302\240 \302\240 /* put the TZIC into the reset value with\n" + "> > + \302\240 \302\240 \302\240 \302\240* all interrupts disabled\n" + "> > + \302\240 \302\240 \302\240 \302\240*/\n" + "> > + \302\240 \302\240 \302\240 i = __raw_readl(tzic_base + TZIC_INTCNTL);\n" "> \n" "> Mixing the use of 'i' as both a signed counter and register value might\n" "> not be a good idea, provided it's not guaranteed from theory that 'i' as\n" @@ -243,12 +253,12 @@ "Fair enough.\n" "\n" "> > +\n" - "> > + ? ? ? __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);\n" - "> > + ? ? ? i = __raw_readl(tzic_base + TZIC_INTCNTL);\n" - "> > + ? ? ? __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);\n" - "> > + ? ? ? i = __raw_readl(tzic_base + TZIC_PRIOMASK);\n" - "> > + ? ? ? __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);\n" - "> > + ? ? ? i = __raw_readl(tzic_base + TZIC_SYNCCTRL);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);\n" + "> > + \302\240 \302\240 \302\240 i = __raw_readl(tzic_base + TZIC_INTCNTL);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);\n" + "> > + \302\240 \302\240 \302\240 i = __raw_readl(tzic_base + TZIC_PRIOMASK);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);\n" + "> > + \302\240 \302\240 \302\240 i = __raw_readl(tzic_base + TZIC_SYNCCTRL);\n" "> \n" "> Are these read-back really necessary? We can start without them and add them\n" "> later if they do cause issues.\n" @@ -258,22 +268,22 @@ "I'll remove it for now to see what happens in my testing.\n" "\n" "> > +\n" - "> > + ? ? ? for (i = 0; i < 4; i++)\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0 + i * 4);\n" + "> > + \302\240 \302\240 \302\240 for (i = 0; i < 4; i++)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0 + i * 4);\n" "> > +\n" - "> > + ? ? ? /* disable all interrupts */\n" - "> > + ? ? ? for (i = 0; i < 4; i++)\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0 + i * 4);\n" + "> > + \302\240 \302\240 \302\240 /* disable all interrupts */\n" + "> > + \302\240 \302\240 \302\240 for (i = 0; i < 4; i++)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0 + i * 4);\n" "> > +\n" - "> > + ? ? ? /* all IRQ no FIQ Warning :: No selection */\n" + "> > + \302\240 \302\240 \302\240 /* all IRQ no FIQ Warning :: No selection */\n" "> > +\n" - "> > + ? ? ? for (i = 0; i < MXC_INTERNAL_IRQS; i++) {\n" - "> > + ? ? ? ? ? ? ? set_irq_chip(i, &mxc_tzic_chip);\n" - "> > + ? ? ? ? ? ? ? set_irq_handler(i, handle_level_irq);\n" - "> > + ? ? ? ? ? ? ? set_irq_flags(i, IRQF_VALID);\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 set_irq_chip(i, &mxc_tzic_chip);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 set_irq_handler(i, handle_level_irq);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 set_irq_flags(i, IRQF_VALID);\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" - "> > + ? ? ? printk(KERN_INFO \"TrustZone Interrupt Controller (TZIC) initialized\\n\");\n" + "> > + \302\240 \302\240 \302\240 printk(KERN_INFO \"TrustZone Interrupt Controller (TZIC) initialized\\n\");\n" "> \n" "> You may want to use pr_info() for short.\n" "\n" @@ -284,35 +294,35 @@ "> > +/*\n" "> > + * enable wakeup interrupt\n" "> > + *\n" - "> > + * @param is_idle ? ? ? ? ? ? ?1 if called in idle loop (ENSET register);\n" - "> > + * ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 to be used when called from low power entry\n" - "> > + * @return ? ? ? ? ? ? ? ? ? ? 0 if successful; non-zero otherwise\n" + "> > + * @param is_idle \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2401 if called in idle loop (ENSET register);\n" + "> > + * \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 to be used when called from low power entry\n" + "> > + * @return \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 if successful; non-zero otherwise\n" "> > + *\n" "> > + */\n" "> > +int tzic_enable_wake(int is_idle)\n" "> > +{\n" - "> > + ? ? ? unsigned int i, v;\n" + "> > + \302\240 \302\240 \302\240 unsigned int i, v;\n" "> > +\n" - "> > + ? ? ? __raw_writel(1, tzic_base + TZIC_DSMINT);\n" - "> > + ? ? ? if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))\n" - "> > + ? ? ? ? ? ? ? return -EAGAIN;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(1, tzic_base + TZIC_DSMINT);\n" + "> > + \302\240 \302\240 \302\240 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EAGAIN;\n" "> \n" "> Looks like an unnecessary read-back provided the silicon is sane enough.\n" "\n" "Again, Dinh/Rob can you comment?\n" "\n" "> > +\n" - "> > + ? ? ? if (likely(is_idle)) {\n" - "> > + ? ? ? ? ? ? ? for (i = 0; i < 4; i++) {\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? v = __raw_readl(tzic_base + TZIC_ENSET0 + i * 4);\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);\n" - "> > + ? ? ? ? ? ? ? }\n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? for (i = 0; i < 4; i++) {\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? v = wakeup_intr[i];\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);\n" - "> > + ? ? ? ? ? ? ? }\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 if (likely(is_idle)) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 for (i = 0; i < 4; i++) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 v = __raw_readl(tzic_base + TZIC_ENSET0 + i * 4);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 for (i = 0; i < 4; i++) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 v = wakeup_intr[i];\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(v, tzic_base + TZIC_WAKEUP0 + i * 4);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 }\n" "> \n" "> Or could be simplified to:\n" "> \n" @@ -325,7 +335,7 @@ "\n" "> but just nit-picking comments, so it's up to you.\n" "> \n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> \n" "> Mmmm.... this being called elsewhere, I'm thinking about making this a\n" @@ -339,7 +349,7 @@ "/Amit\n" "-- \n" "----------------------------------------------------------------------\n" - "Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com\n" + "Amit Kucheria, Kernel Engineer || amit.kucheria@canonical.com\n" ---------------------------------------------------------------------- -a8a94762b42b88f96e60c1c33466a2284e8a1087d5d0b86f1c2b9a81f5964e04 +d2bb32e400f87c004e35a6144fa13b80919005e08b0b877c17eeea44d3bf72cb
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