diff for duplicates of <20100203142015.GE5252@k2> diff --git a/a/1.txt b/N1/1.txt index 12f1d9a..5b0494b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,25 +7,25 @@ On 10 Feb 02, Eric Miao wrote: > > > > Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com> > > --- -> > ?arch/arm/mach-mx5/clock.c ? ? ? ? ? ? ? ? ? ?| ?848 ++++++++++++++++++++++++++ -> > ?arch/arm/mach-mx5/cpu.c ? ? ? ? ? ? ? ? ? ? ?| ? 45 ++ -> > ?arch/arm/mach-mx5/crm_regs.h ? ? ? ? ? ? ? ? | ?583 ++++++++++++++++++ -> > ?arch/arm/mach-mx5/devices.c ? ? ? ? ? ? ? ? ?| ? 96 +++ -> > ?arch/arm/mach-mx5/devices.h ? ? ? ? ? ? ? ? ?| ? ?4 + -> > ?arch/arm/mach-mx5/mm.c ? ? ? ? ? ? ? ? ? ? ? | ? 88 +++ -> > ?arch/arm/plat-mxc/include/mach/common.h ? ? ?| ? ?1 + -> > ?arch/arm/plat-mxc/include/mach/debug-macro.S | ? ?4 +- -> > ?arch/arm/plat-mxc/include/mach/iomux-mx51.h ?| ?340 +++++++++++ -> > ?arch/arm/plat-mxc/include/mach/mx51.h ? ? ? ?| ?454 ++++++++++++++ -> > ?10 files changed, 2461 insertions(+), 2 deletions(-) -> > ?create mode 100644 arch/arm/mach-mx5/clock.c -> > ?create mode 100644 arch/arm/mach-mx5/cpu.c -> > ?create mode 100644 arch/arm/mach-mx5/crm_regs.h -> > ?create mode 100644 arch/arm/mach-mx5/devices.c -> > ?create mode 100644 arch/arm/mach-mx5/devices.h -> > ?create mode 100644 arch/arm/mach-mx5/mm.c -> > ?create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h -> > ?create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h +> > arch/arm/mach-mx5/clock.c | 848 ++++++++++++++++++++++++++ +> > arch/arm/mach-mx5/cpu.c | 45 ++ +> > arch/arm/mach-mx5/crm_regs.h | 583 ++++++++++++++++++ +> > arch/arm/mach-mx5/devices.c | 96 +++ +> > arch/arm/mach-mx5/devices.h | 4 + +> > arch/arm/mach-mx5/mm.c | 88 +++ +> > arch/arm/plat-mxc/include/mach/common.h | 1 + +> > arch/arm/plat-mxc/include/mach/debug-macro.S | 4 +- +> > arch/arm/plat-mxc/include/mach/iomux-mx51.h | 340 +++++++++++ +> > arch/arm/plat-mxc/include/mach/mx51.h | 454 ++++++++++++++ +> > 10 files changed, 2461 insertions(+), 2 deletions(-) +> > create mode 100644 arch/arm/mach-mx5/clock.c +> > create mode 100644 arch/arm/mach-mx5/cpu.c +> > create mode 100644 arch/arm/mach-mx5/crm_regs.h +> > create mode 100644 arch/arm/mach-mx5/devices.c +> > create mode 100644 arch/arm/mach-mx5/devices.h +> > create mode 100644 arch/arm/mach-mx5/mm.c +> > create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h +> > create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h > > > > diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c > > new file mode 100644 @@ -59,9 +59,9 @@ On 10 Feb 02, Eric Miao wrote: > > +#include "crm_regs.h" > > + > > +static void __iomem *pll_base[] = { -> > + ? ? ? MX51_DPLL1_BASE, -> > + ? ? ? MX51_DPLL2_BASE, -> > + ? ? ? MX51_DPLL3_BASE, +> > + MX51_DPLL1_BASE, +> > + MX51_DPLL2_BASE, +> > + MX51_DPLL3_BASE, > > +}; > > + > > +/* External clock values passed-in by the board code */ @@ -78,184 +78,184 @@ On 10 Feb 02, Eric Miao wrote: > > +static struct clk ahb_clk; > > +static struct clk ipg_clk; > > + -> > +#define MAX_DPLL_WAIT_TRIES ? ?1000 /* 1000 * udelay(1) = 1ms */ +> > +#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ > > + > > +static int _clk_ccgr_enable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(clk->enable_reg); -> > + ? ? ? reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; -> > + ? ? ? __raw_writel(reg, clk->enable_reg); +> > + reg = __raw_readl(clk->enable_reg); +> > + reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; +> > + __raw_writel(reg, clk->enable_reg); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static void _clk_ccgr_disable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; -> > + ? ? ? reg = __raw_readl(clk->enable_reg); -> > + ? ? ? reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); -> > + ? ? ? __raw_writel(reg, clk->enable_reg); +> > + u32 reg; +> > + reg = __raw_readl(clk->enable_reg); +> > + reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); +> > + __raw_writel(reg, clk->enable_reg); > > + > > +} > > + > > +static void _clk_ccgr_disable_inwait(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(clk->enable_reg); -> > + ? ? ? reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); -> > + ? ? ? reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; -> > + ? ? ? __raw_writel(reg, clk->enable_reg); +> > + reg = __raw_readl(clk->enable_reg); +> > + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); +> > + reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; +> > + __raw_writel(reg, clk->enable_reg); > > +} > > + > > +/* > > + * For the 4-to-1 muxed input clock > > + */ > > +static inline u32 _get_mux(struct clk *parent, struct clk *m0, -> > + ? ? ? ? ? ? ? ? ? ? ? ? ?struct clk *m1, struct clk *m2, struct clk *m3) +> > + struct clk *m1, struct clk *m2, struct clk *m3) > > +{ -> > + ? ? ? if (parent == m0) -> > + ? ? ? ? ? ? ? return 0; -> > + ? ? ? else if (parent == m1) -> > + ? ? ? ? ? ? ? return 1; -> > + ? ? ? else if (parent == m2) -> > + ? ? ? ? ? ? ? return 2; -> > + ? ? ? else if (parent == m3) -> > + ? ? ? ? ? ? ? return 3; -> > + ? ? ? else -> > + ? ? ? ? ? ? ? BUG(); -> > + -> > + ? ? ? return -EINVAL; +> > + if (parent == m0) +> > + return 0; +> > + else if (parent == m1) +> > + return 1; +> > + else if (parent == m2) +> > + return 2; +> > + else if (parent == m3) +> > + return 3; +> > + else +> > + BUG(); +> > + +> > + return -EINVAL; > > +} > > + > > +static inline void __iomem *_get_pll_base(struct clk *pll) > > +{ -> > + ? ? ? if (pll == &pll1_main_clk) -> > + ? ? ? ? ? ? ? return pll_base[0]; -> > + ? ? ? else if (pll == &pll2_sw_clk) -> > + ? ? ? ? ? ? ? return pll_base[1]; -> > + ? ? ? else if (pll == &pll3_sw_clk) -> > + ? ? ? ? ? ? ? return pll_base[2]; -> > + ? ? ? else -> > + ? ? ? ? ? ? ? BUG(); -> > + -> > + ? ? ? return NULL; +> > + if (pll == &pll1_main_clk) +> > + return pll_base[0]; +> > + else if (pll == &pll2_sw_clk) +> > + return pll_base[1]; +> > + else if (pll == &pll3_sw_clk) +> > + return pll_base[2]; +> > + else +> > + BUG(); +> > + +> > + return NULL; > > +} > > + > > +static unsigned long clk_pll_get_rate(struct clk *clk) > > +{ -> > + ? ? ? long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; -> > + ? ? ? unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; -> > + ? ? ? void __iomem *pllbase; -> > + ? ? ? s64 temp; -> > + ? ? ? unsigned long parent_rate; -> > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + -> > + ? ? ? pllbase = _get_pll_base(clk); -> > + -> > + ? ? ? dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); -> > + ? ? ? pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; -> > + ? ? ? dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; -> > + -> > + ? ? ? if (pll_hfsm == 0) { -> > + ? ? ? ? ? ? ? dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); -> > + ? ? ? ? ? ? ? dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); -> > + ? ? ? ? ? ? ? dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); -> > + ? ? ? ? ? ? ? dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); -> > + ? ? ? ? ? ? ? dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); -> > + ? ? ? } -> > + ? ? ? pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; -> > + ? ? ? mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; -> > + ? ? ? mfi = (mfi <= 5) ? 5 : mfi; -> > + ? ? ? mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; -> > + ? ? ? mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; -> > + ? ? ? /* Sign extend to 32-bits */ -> > + ? ? ? if (mfn >= 0x04000000) { -> > + ? ? ? ? ? ? ? mfn |= 0xFC000000; -> > + ? ? ? ? ? ? ? mfn_abs = -mfn; -> > + ? ? ? } -> > + -> > + ? ? ? ref_clk = 2 * parent_rate; -> > + ? ? ? if (dbl != 0) -> > + ? ? ? ? ? ? ? ref_clk *= 2; -> > + -> > + ? ? ? ref_clk /= (pdf + 1); -> > + ? ? ? temp = (u64) ref_clk * mfn_abs; -> > + ? ? ? do_div(temp, mfd + 1); -> > + ? ? ? if (mfn < 0) -> > + ? ? ? ? ? ? ? temp = -temp; -> > + ? ? ? temp = (ref_clk * mfi) + temp; -> > + -> > + ? ? ? return temp; +> > + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; +> > + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; +> > + void __iomem *pllbase; +> > + s64 temp; +> > + unsigned long parent_rate; +> > + +> > + parent_rate = clk_get_rate(clk->parent); +> > + +> > + pllbase = _get_pll_base(clk); +> > + +> > + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); +> > + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; +> > + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; +> > + +> > + if (pll_hfsm == 0) { +> > + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); +> > + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); +> > + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); +> > + } else { +> > + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); +> > + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); +> > + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); +> > + } +> > + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; +> > + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; +> > + mfi = (mfi <= 5) ? 5 : mfi; +> > + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; +> > + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; +> > + /* Sign extend to 32-bits */ +> > + if (mfn >= 0x04000000) { +> > + mfn |= 0xFC000000; +> > + mfn_abs = -mfn; +> > + } +> > + +> > + ref_clk = 2 * parent_rate; +> > + if (dbl != 0) +> > + ref_clk *= 2; +> > + +> > + ref_clk /= (pdf + 1); +> > + temp = (u64) ref_clk * mfn_abs; +> > + do_div(temp, mfd + 1); +> > + if (mfn < 0) +> > + temp = -temp; +> > + temp = (ref_clk * mfi) + temp; +> > + +> > + return temp; > > +} > > + > > +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) > > +{ -> > + ? ? ? u32 reg; -> > + ? ? ? void __iomem *pllbase; -> > + -> > + ? ? ? long mfi, pdf, mfn, mfd = 999999; -> > + ? ? ? s64 temp64; -> > + ? ? ? unsigned long quad_parent_rate; -> > + ? ? ? unsigned long pll_hfsm, dp_ctl; -> > + ? ? ? unsigned long parent_rate; -> > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + -> > + ? ? ? pllbase = _get_pll_base(clk); -> > + -> > + ? ? ? quad_parent_rate = 4 * parent_rate; -> > + ? ? ? pdf = mfi = -1; -> > + ? ? ? while (++pdf < 16 && mfi < 5) -> > + ? ? ? ? ? ? ? mfi = rate * (pdf+1) / quad_parent_rate; -> > + ? ? ? if (mfi > 15) -> > + ? ? ? ? ? ? ? return -1; -> > + ? ? ? pdf--; -> > + -> > + ? ? ? temp64 = rate * (pdf+1) - quad_parent_rate * mfi; -> > + ? ? ? do_div(temp64, quad_parent_rate/1000000); -> > + ? ? ? mfn = (long)temp64; -> > + -> > + ? ? ? dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); -> > + ? ? ? /* use dpdck0_2 */ -> > + ? ? ? __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); -> > + ? ? ? pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; -> > + ? ? ? if (pll_hfsm == 0) { -> > + ? ? ? ? ? ? ? reg = mfi << 4 | pdf; -> > + ? ? ? ? ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_OP); -> > + ? ? ? ? ? ? ? __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); -> > + ? ? ? ? ? ? ? __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? reg = mfi << 4 | pdf; -> > + ? ? ? ? ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); -> > + ? ? ? ? ? ? ? __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); -> > + ? ? ? ? ? ? ? __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); -> > + ? ? ? } -> > + -> > + ? ? ? return 0; +> > + u32 reg; +> > + void __iomem *pllbase; +> > + +> > + long mfi, pdf, mfn, mfd = 999999; +> > + s64 temp64; +> > + unsigned long quad_parent_rate; +> > + unsigned long pll_hfsm, dp_ctl; +> > + unsigned long parent_rate; +> > + +> > + parent_rate = clk_get_rate(clk->parent); +> > + +> > + pllbase = _get_pll_base(clk); +> > + +> > + quad_parent_rate = 4 * parent_rate; +> > + pdf = mfi = -1; +> > + while (++pdf < 16 && mfi < 5) +> > + mfi = rate * (pdf+1) / quad_parent_rate; +> > + if (mfi > 15) +> > + return -1; +> > + pdf--; +> > + +> > + temp64 = rate * (pdf+1) - quad_parent_rate * mfi; +> > + do_div(temp64, quad_parent_rate/1000000); +> > + mfn = (long)temp64; +> > + +> > + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); +> > + /* use dpdck0_2 */ +> > + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); +> > + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; +> > + if (pll_hfsm == 0) { +> > + reg = mfi << 4 | pdf; +> > + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); +> > + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); +> > + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); +> > + } else { +> > + reg = mfi << 4 | pdf; +> > + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); +> > + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); +> > + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); +> > + } +> > + +> > + return 0; > > +} > > + > > +static int _clk_pll_enable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; -> > + ? ? ? void __iomem *pllbase; -> > + ? ? ? int i = 0; -> > + -> > + ? ? ? pllbase = _get_pll_base(clk); -> > + ? ? ? reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; -> > + ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); -> > + -> > + ? ? ? /* Wait for lock */ -> > + ? ? ? while ((!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) -> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? i++; -> > + ? ? ? ? ? ? ? udelay(1); -> > + ? ? ? } +> > + u32 reg; +> > + void __iomem *pllbase; +> > + int i = 0; +> > + +> > + pllbase = _get_pll_base(clk); +> > + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; +> > + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +> > + +> > + /* Wait for lock */ +> > + while ((!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) +> > + && i < MAX_DPLL_WAIT_TRIES) { +> > + i++; +> > + udelay(1); +> > + } > > > Mmm... this really hurts my eyes: @@ -272,65 +272,65 @@ On 10 Feb 02, Eric Miao wrote: (Shrug) I picked it up from OMAP code. But your style is better. > > + -> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? printk(KERN_ERR "MX5: pll locking failed\n"); -> > + ? ? ? ? ? ? ? return -EINVAL; -> > + ? ? ? } +> > + if (i == MAX_DPLL_WAIT_TRIES) { +> > + printk(KERN_ERR "MX5: pll locking failed\n"); +> > + return -EINVAL; +> > + } > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static void _clk_pll_disable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; -> > + ? ? ? void __iomem *pllbase; +> > + u32 reg; +> > + void __iomem *pllbase; > > + -> > + ? ? ? pllbase = _get_pll_base(clk); -> > + ? ? ? reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; -> > + ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +> > + pllbase = _get_pll_base(clk); +> > + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; +> > + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); > > +} > > + > > +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR); +> > + reg = __raw_readl(MXC_CCM_CCSR); > > + -> > + ? ? ? /* When switching from pll_main_clk to a bypass clock, first select a -> > + ? ? ? ? ?multiplexed clock in 'step_sel', then shift the glitchless mux -> > + ? ? ? ? ?'pll1_sw_clk_sel'. -> > + ? ? ? ? ?When switching back, do it in reverse order -> > + ? ? ? */ +> > + /* When switching from pll_main_clk to a bypass clock, first select a +> > + multiplexed clock in 'step_sel', then shift the glitchless mux +> > + 'pll1_sw_clk_sel'. +> > + When switching back, do it in reverse order +> > + */ > > comment style ... not sure if this leaks apw's checkscripts, heh :) The patch was checkpatch approved ;) But will fix. -> > + ? ? ? if (parent == &pll1_main_clk) { -> > + ? ? ? ? ? ? ? /* Switch to pll1_main_clk */ -> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; -> > + ? ? ? ? ? ? ? __raw_writel(reg, MXC_CCM_CCSR); -> > + ? ? ? ? ? ? ? /* step_clk mux switched to lp_apm, to save power. */ -> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR); -> > + ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | -> > + ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_LP_APM << -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET); -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? if (parent == &lp_apm_clk) { -> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_LP_APM << -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET); -> > + ? ? ? ? ? ? ? } else ?if (parent == &pll2_sw_clk) { -> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED << -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET); -> > + ? ? ? ? ? ? ? } else ?if (parent == &pll3_sw_clk) { -> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED << -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET); -> > + ? ? ? ? ? ? ? } else -> > + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL; +> > + if (parent == &pll1_main_clk) { +> > + /* Switch to pll1_main_clk */ +> > + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; +> > + __raw_writel(reg, MXC_CCM_CCSR); +> > + /* step_clk mux switched to lp_apm, to save power. */ +> > + reg = __raw_readl(MXC_CCM_CCSR); +> > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | +> > + (MXC_CCM_CCSR_STEP_SEL_LP_APM << +> > + MXC_CCM_CCSR_STEP_SEL_OFFSET); +> > + } else { +> > + if (parent == &lp_apm_clk) { +> > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | +> > + (MXC_CCM_CCSR_STEP_SEL_LP_APM << +> > + MXC_CCM_CCSR_STEP_SEL_OFFSET); +> > + } else if (parent == &pll2_sw_clk) { +> > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | +> > + (MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED << +> > + MXC_CCM_CCSR_STEP_SEL_OFFSET); +> > + } else if (parent == &pll3_sw_clk) { +> > + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | +> > + (MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED << +> > + MXC_CCM_CCSR_STEP_SEL_OFFSET); +> > + } else +> > + return -EINVAL; > > Again, hurts my eyes: > @@ -348,168 +348,168 @@ But will fix. Fixed. > > + -> > + ? ? ? ? ? ? ? __raw_writel(reg, MXC_CCM_CCSR); -> > + ? ? ? ? ? ? ? /* Switch to step_clk */ -> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR); -> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; -> > + ? ? ? } -> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR); -> > + ? ? ? return 0; +> > + __raw_writel(reg, MXC_CCM_CCSR); +> > + /* Switch to step_clk */ +> > + reg = __raw_readl(MXC_CCM_CCSR); +> > + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; +> > + } +> > + __raw_writel(reg, MXC_CCM_CCSR); +> > + return 0; > > +} > > + > > +static unsigned long clk_pll1_sw_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 reg, div; -> > + ? ? ? unsigned long parent_rate; -> > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + -> > + ? ? ? div = 1; -> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR); -> > + -> > + ? ? ? if (clk->parent == &pll2_sw_clk) { -> > + ? ? ? ? ? ? ? div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> -> > + ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; -> > + ? ? ? } else if (clk->parent == &pll3_sw_clk) { -> > + ? ? ? ? ? ? ? div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> -> > + ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; -> > + ? ? ? } -> > + ? ? ? return parent_rate / div; +> > + u32 reg, div; +> > + unsigned long parent_rate; +> > + +> > + parent_rate = clk_get_rate(clk->parent); +> > + +> > + div = 1; +> > + reg = __raw_readl(MXC_CCM_CCSR); +> > + +> > + if (clk->parent == &pll2_sw_clk) { +> > + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> +> > + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; +> > + } else if (clk->parent == &pll3_sw_clk) { +> > + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> +> > + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; +> > + } +> > + return parent_rate / div; > > +} > > + > > +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR); +> > + reg = __raw_readl(MXC_CCM_CCSR); > > + -> > + ? ? ? if (parent == &pll2_sw_clk) -> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; -> > + ? ? ? else -> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; +> > + if (parent == &pll2_sw_clk) +> > + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; +> > + else +> > + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; > > + -> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR); -> > + ? ? ? return 0; +> > + __raw_writel(reg, MXC_CCM_CCSR); +> > + return 0; > > +} > > + > > +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? if (parent == &osc_clk) -> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; -> > + ? ? ? else -> > + ? ? ? ? ? ? ? return -EINVAL; +> > + if (parent == &osc_clk) +> > + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; +> > + else +> > + return -EINVAL; > > + -> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR); +> > + __raw_writel(reg, MXC_CCM_CCSR); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static unsigned long clk_arm_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 cacrr, div; -> > + ? ? ? unsigned long parent_rate; +> > + u32 cacrr, div; +> > + unsigned long parent_rate; > > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + ? ? ? cacrr = __raw_readl(MXC_CCM_CACRR); -> > + ? ? ? div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; +> > + parent_rate = clk_get_rate(clk->parent); +> > + cacrr = __raw_readl(MXC_CCM_CACRR); +> > + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; > > + -> > + ? ? ? return parent_rate / div; +> > + return parent_rate / div; > > +} > > + > > +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg, mux; -> > + ? ? ? int i = 0; +> > + u32 reg, mux; +> > + int i = 0; > > + -> > + ? ? ? mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); +> > + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; -> > + ? ? ? reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; -> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCMR); +> > + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; +> > + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; +> > + __raw_writel(reg, MXC_CCM_CBCMR); > > + -> > + ? ? ? /* Wait for lock */ -> > + ? ? ? while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) -> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? i++; -> > + ? ? ? ? ? ? ? udelay(1); -> > + ? ? ? } +> > + /* Wait for lock */ +> > + while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) +> > + && i < MAX_DPLL_WAIT_TRIES) { +> > + i++; +> > + udelay(1); +> > + } > > + -> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? printk(KERN_ERR "MX5: Set parent for periph_apm clock failed\n"); -> > + ? ? ? ? ? ? ? return -EINVAL; -> > + ? ? ? } +> > + if (i == MAX_DPLL_WAIT_TRIES) { +> > + printk(KERN_ERR "MX5: Set parent for periph_apm clock failed\n"); +> > + return -EINVAL; +> > + } > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static unsigned long clk_main_bus_get_rate(struct clk *clk) > > +{ -> > + ? ? ? return clk_get_rate(clk->parent); +> > + return clk_get_rate(clk->parent); > > +} > > + > > +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); +> > + reg = __raw_readl(MXC_CCM_CBCDR); > > + -> > + ? ? ? if (parent == &pll2_sw_clk) -> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; -> > + ? ? ? else if (parent == &periph_apm_clk) -> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; -> > + ? ? ? else -> > + ? ? ? ? ? ? ? return -EINVAL; +> > + if (parent == &pll2_sw_clk) +> > + reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; +> > + else if (parent == &periph_apm_clk) +> > + reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; +> > + else +> > + return -EINVAL; > > + -> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR); +> > + __raw_writel(reg, MXC_CCM_CBCDR); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static struct clk main_bus_clk = { -> > + ? ? ? .parent = &pll2_sw_clk, -> > + ? ? ? .set_parent = _clk_main_bus_set_parent, -> > + ? ? ? .get_rate = clk_main_bus_get_rate, +> > + .parent = &pll2_sw_clk, +> > + .set_parent = _clk_main_bus_set_parent, +> > + .get_rate = clk_main_bus_get_rate, > > +}; > > + > > +static unsigned long clk_ahb_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 reg, div; -> > + ? ? ? unsigned long parent_rate; +> > + u32 reg, div; +> > + unsigned long parent_rate; > > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); +> > + parent_rate = clk_get_rate(clk->parent); > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); -> > + ? ? ? div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> -> > + ? ? ? ? ? ? ?MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; -> > + ? ? ? return parent_rate / div; +> > + reg = __raw_readl(MXC_CCM_CBCDR); +> > + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> +> > + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; +> > + return parent_rate / div; > > +} > > + > > + > > +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) > > +{ -> > + ? ? ? u32 reg, div; -> > + ? ? ? unsigned long parent_rate; -> > + ? ? ? int i = 0; -> > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + -> > + ? ? ? div = parent_rate / rate; -> > + ? ? ? if (div > 8 || div < 1 || ((parent_rate / div) != rate)) -> > + ? ? ? ? ? ? ? return -EINVAL; -> > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); -> > + ? ? ? reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; -> > + ? ? ? reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; -> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR); -> > + -> > + ? ? ? /* Wait for lock */ -> > + ? ? ? while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) -> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? i++; -> > + ? ? ? ? ? ? ? udelay(1); -> > + ? ? ? } +> > + u32 reg, div; +> > + unsigned long parent_rate; +> > + int i = 0; +> > + +> > + parent_rate = clk_get_rate(clk->parent); +> > + +> > + div = parent_rate / rate; +> > + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) +> > + return -EINVAL; +> > + +> > + reg = __raw_readl(MXC_CCM_CBCDR); +> > + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; +> > + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; +> > + __raw_writel(reg, MXC_CCM_CBCDR); +> > + +> > + /* Wait for lock */ +> > + while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) +> > + && i < MAX_DPLL_WAIT_TRIES) { +> > + i++; +> > + udelay(1); +> > + } > > Provided this loop sequence appears so many times here, maybe we can just > invent a static inline function for this, e.g. dpll_wait_flags(register, flags) @@ -517,187 +517,187 @@ Fixed. Will investigate. > > + -> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) { -> > + ? ? ? ? ? ? ? printk(KERN_ERR "MX5: clk_ahb_set_rate failed\n"); -> > + ? ? ? ? ? ? ? return -EINVAL; -> > + ? ? ? } +> > + if (i == MAX_DPLL_WAIT_TRIES) { +> > + printk(KERN_ERR "MX5: clk_ahb_set_rate failed\n"); +> > + return -EINVAL; +> > + } > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static unsigned long _clk_ahb_round_rate(struct clk *clk, -> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long rate) +> > + unsigned long rate) > > +{ -> > + ? ? ? u32 div; -> > + ? ? ? unsigned long parent_rate; +> > + u32 div; +> > + unsigned long parent_rate; > > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); +> > + parent_rate = clk_get_rate(clk->parent); > > + -> > + ? ? ? div = parent_rate / rate; -> > + ? ? ? if (div > 8) -> > + ? ? ? ? ? ? ? div = 8; -> > + ? ? ? else if (div == 0) -> > + ? ? ? ? ? ? ? div++; -> > + ? ? ? return parent_rate / div; +> > + div = parent_rate / rate; +> > + if (div > 8) +> > + div = 8; +> > + else if (div == 0) +> > + div++; +> > + return parent_rate / div; > > +} > > + > > + > > +static int _clk_max_enable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? _clk_ccgr_enable(clk); +> > + _clk_ccgr_enable(clk); > > + -> > + ? ? ? /* Handshake with MAX when LPM is entered. */ -> > + ? ? ? reg = __raw_readl(MXC_CCM_CLPCR); -> > + ? ? ? reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; -> > + ? ? ? __raw_writel(reg, MXC_CCM_CLPCR); +> > + /* Handshake with MAX when LPM is entered. */ +> > + reg = __raw_readl(MXC_CCM_CLPCR); +> > + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; +> > + __raw_writel(reg, MXC_CCM_CLPCR); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static void _clk_max_disable(struct clk *clk) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? _clk_ccgr_disable_inwait(clk); +> > + _clk_ccgr_disable_inwait(clk); > > + -> > + ? ? ? /* No Handshake with MAX when LPM is entered as its disabled. */ -> > + ? ? ? reg = __raw_readl(MXC_CCM_CLPCR); -> > + ? ? ? reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; -> > + ? ? ? __raw_writel(reg, MXC_CCM_CLPCR); +> > + /* No Handshake with MAX when LPM is entered as its disabled. */ +> > + reg = __raw_readl(MXC_CCM_CLPCR); +> > + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; +> > + __raw_writel(reg, MXC_CCM_CLPCR); > > +} > > + > > +static unsigned long clk_ipg_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 reg, div; -> > + ? ? ? unsigned long parent_rate; +> > + u32 reg, div; +> > + unsigned long parent_rate; > > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); +> > + parent_rate = clk_get_rate(clk->parent); > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); -> > + ? ? ? div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> -> > + ? ? ? ? ? ? ?MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; +> > + reg = __raw_readl(MXC_CCM_CBCDR); +> > + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> +> > + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; > > + -> > + ? ? ? return parent_rate / div; +> > + return parent_rate / div; > > +} > > + > > +static unsigned long clk_ipg_per_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 reg, prediv1, prediv2, podf; -> > + ? ? ? unsigned long parent_rate; -> > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); -> > + -> > + ? ? ? if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { -> > + ? ? ? ? ? ? ? /* the main_bus_clk is the one before the DVFS engine */ -> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); -> > + ? ? ? ? ? ? ? prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> -> > + ? ? ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; -> > + ? ? ? ? ? ? ? prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> -> > + ? ? ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; -> > + ? ? ? ? ? ? ? podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> -> > + ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; -> > + ? ? ? ? ? ? ? return parent_rate / (prediv1 * prediv2 * podf); -> > + ? ? ? } else if (clk->parent == &ipg_clk) { -> > + ? ? ? ? ? ? ? return parent_rate; +> > + u32 reg, prediv1, prediv2, podf; +> > + unsigned long parent_rate; +> > + +> > + parent_rate = clk_get_rate(clk->parent); +> > + +> > + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { +> > + /* the main_bus_clk is the one before the DVFS engine */ +> > + reg = __raw_readl(MXC_CCM_CBCDR); +> > + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> +> > + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; +> > + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> +> > + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; +> > + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> +> > + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; +> > + return parent_rate / (prediv1 * prediv2 * podf); +> > + } else if (clk->parent == &ipg_clk) { +> > + return parent_rate; > > unnecessary braces > -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? BUG(); +> > + } else { +> > + BUG(); > > ditto > -> > + ? ? ? } +> > + } > > +} > > + > > +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg; +> > + u32 reg; > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR); +> > + reg = __raw_readl(MXC_CCM_CBCMR); > > + -> > + ? ? ? reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; -> > + ? ? ? reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; +> > + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; +> > + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; > > + -> > + ? ? ? if (parent == &ipg_clk) -> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; -> > + ? ? ? else if (parent == &lp_apm_clk) -> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; -> > + ? ? ? else if (parent != &main_bus_clk) -> > + ? ? ? ? ? ? ? return -EINVAL; +> > + if (parent == &ipg_clk) +> > + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; +> > + else if (parent == &lp_apm_clk) +> > + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; +> > + else if (parent != &main_bus_clk) +> > + return -EINVAL; > > + -> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCMR); +> > + __raw_writel(reg, MXC_CCM_CBCMR); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static unsigned long clk_uart_get_rate(struct clk *clk) > > +{ -> > + ? ? ? u32 reg, prediv, podf; -> > + ? ? ? unsigned long parent_rate; +> > + u32 reg, prediv, podf; +> > + unsigned long parent_rate; > > + -> > + ? ? ? parent_rate = clk_get_rate(clk->parent); +> > + parent_rate = clk_get_rate(clk->parent); > > + -> > + ? ? ? reg = __raw_readl(MXC_CCM_CSCDR1); -> > + ? ? ? prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> -> > + ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; -> > + ? ? ? podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> -> > + ? ? ? ? ? ? ? MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; +> > + reg = __raw_readl(MXC_CCM_CSCDR1); +> > + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> +> > + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; +> > + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> +> > + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; > > + -> > + ? ? ? return parent_rate / (prediv * podf); +> > + return parent_rate / (prediv * podf); > > +} > > + > > +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) > > +{ -> > + ? ? ? u32 reg, mux; +> > + u32 reg, mux; > > + -> > + ? ? ? mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, -> > + ? ? ? ? ? ? ? ? ? ? ?&lp_apm_clk); -> > + ? ? ? reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; -> > + ? ? ? reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; -> > + ? ? ? __raw_writel(reg, MXC_CCM_CSCMR1); +> > + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, +> > + &lp_apm_clk); +> > + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; +> > + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; +> > + __raw_writel(reg, MXC_CCM_CSCMR1); > > + -> > + ? ? ? return 0; +> > + return 0; > > +} > > + > > +static unsigned long get_high_reference_clock_rate(struct clk *clk) > > +{ -> > + ? ? ? return external_high_reference; +> > + return external_high_reference; > > +} > > + > > +static unsigned long get_low_reference_clock_rate(struct clk *clk) > > +{ -> > + ? ? ? return external_low_reference; +> > + return external_low_reference; > > +} > > + > > +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) > > +{ -> > + ? ? ? return oscillator_reference; +> > + return oscillator_reference; > > +} > > + > > +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) > > +{ -> > + ? ? ? return ckih2_reference; +> > + return ckih2_reference; > > +} > > + > > +/* External high frequency clock */ > > +static struct clk ckih_clk = { -> > + ? ? ? .get_rate = get_high_reference_clock_rate, +> > + .get_rate = get_high_reference_clock_rate, > > +}; > > + > > +static struct clk ckih2_clk = { -> > + ? ? ? .get_rate = get_ckih2_reference_clock_rate, +> > + .get_rate = get_ckih2_reference_clock_rate, > > +}; > > + > > +static struct clk osc_clk = { -> > + ? ? ? .get_rate = get_oscillator_reference_clock_rate, +> > + .get_rate = get_oscillator_reference_clock_rate, > > +}; > > + > > +/* External low frequency (32kHz) clock */ > > +static struct clk ckil_clk = { -> > + ? ? ? .get_rate = get_low_reference_clock_rate, +> > + .get_rate = get_low_reference_clock_rate, > > +}; > > That's why Jerremy is coming up with a clk_fixed, to address exactly such @@ -707,234 +707,234 @@ Heh, yes :) > > + > > +static struct clk pll1_main_clk = { -> > + ? ? ? .parent = &osc_clk, -> > + ? ? ? .get_rate = clk_pll_get_rate, -> > + ? ? ? .enable = _clk_pll_enable, -> > + ? ? ? .disable = _clk_pll_disable, +> > + .parent = &osc_clk, +> > + .get_rate = clk_pll_get_rate, +> > + .enable = _clk_pll_enable, +> > + .disable = _clk_pll_disable, > > +}; > > + > > +/* Clock tree block diagram (WIP): -> > + * ? ? CCM: Clock Controller Module +> > + * CCM: Clock Controller Module > > + * > > + * PLL output -> | -> > + * ? ? ? ? ? ? ? | CCM Switcher -> CCM_CLK_ROOT_GEN -> +> > + * | CCM Switcher -> CCM_CLK_ROOT_GEN -> > > + * PLL bypass -> | > > + * > > + */ > > + > > +/* PLL1 SW supplies to ARM core */ > > +static struct clk pll1_sw_clk = { -> > + ? ? ? .parent = &pll1_main_clk, -> > + ? ? ? .set_parent = _clk_pll1_sw_set_parent, -> > + ? ? ? .get_rate = clk_pll1_sw_get_rate, +> > + .parent = &pll1_main_clk, +> > + .set_parent = _clk_pll1_sw_set_parent, +> > + .get_rate = clk_pll1_sw_get_rate, > > +}; > > + > > +/* PLL2 SW supplies to AXI/AHB/IP buses */ > > +static struct clk pll2_sw_clk = { -> > + ? ? ? .parent = &osc_clk, -> > + ? ? ? .get_rate = clk_pll_get_rate, -> > + ? ? ? .set_rate = _clk_pll_set_rate, -> > + ? ? ? .set_parent = _clk_pll2_sw_set_parent, -> > + ? ? ? .enable = _clk_pll_enable, -> > + ? ? ? .disable = _clk_pll_disable, +> > + .parent = &osc_clk, +> > + .get_rate = clk_pll_get_rate, +> > + .set_rate = _clk_pll_set_rate, +> > + .set_parent = _clk_pll2_sw_set_parent, +> > + .enable = _clk_pll_enable, +> > + .disable = _clk_pll_disable, > > +}; > > + > > +/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ > > +static struct clk pll3_sw_clk = { -> > + ? ? ? .parent = &osc_clk, -> > + ? ? ? .set_rate = _clk_pll_set_rate, -> > + ? ? ? .get_rate = clk_pll_get_rate, -> > + ? ? ? .enable = _clk_pll_enable, -> > + ? ? ? .disable = _clk_pll_disable, +> > + .parent = &osc_clk, +> > + .set_rate = _clk_pll_set_rate, +> > + .get_rate = clk_pll_get_rate, +> > + .enable = _clk_pll_enable, +> > + .disable = _clk_pll_disable, > > +}; > > + > > +/* Low-power Audio Playback Mode clock */ > > +static struct clk lp_apm_clk = { -> > + ? ? ? .parent = &osc_clk, -> > + ? ? ? .set_parent = _clk_lp_apm_set_parent, +> > + .parent = &osc_clk, +> > + .set_parent = _clk_lp_apm_set_parent, > > +}; > > + > > +static struct clk periph_apm_clk = { -> > + ? ? ? .parent = &pll1_sw_clk, -> > + ? ? ? .set_parent = _clk_periph_apm_set_parent, +> > + .parent = &pll1_sw_clk, +> > + .set_parent = _clk_periph_apm_set_parent, > > +}; > > + > > +static struct clk cpu_clk = { -> > + ? ? ? .parent = &pll1_sw_clk, -> > + ? ? ? .get_rate = clk_arm_get_rate, +> > + .parent = &pll1_sw_clk, +> > + .get_rate = clk_arm_get_rate, > > +}; > > + > > +static struct clk ahb_clk = { -> > + ? ? ? .parent = &main_bus_clk, -> > + ? ? ? .get_rate = clk_ahb_get_rate, -> > + ? ? ? .set_rate = _clk_ahb_set_rate, -> > + ? ? ? .round_rate = _clk_ahb_round_rate, +> > + .parent = &main_bus_clk, +> > + .get_rate = clk_ahb_get_rate, +> > + .set_rate = _clk_ahb_set_rate, +> > + .round_rate = _clk_ahb_round_rate, > > +}; > > + > > +/* Main IP interface clock for access to registers */ > > +static struct clk ipg_clk = { -> > + ? ? ? .parent = &ahb_clk, -> > + ? ? ? .get_rate = clk_ipg_get_rate, +> > + .parent = &ahb_clk, +> > + .get_rate = clk_ipg_get_rate, > > +}; > > + > > +static struct clk ipg_perclk = { -> > + ? ? ? .parent = &lp_apm_clk, -> > + ? ? ? .get_rate = clk_ipg_per_get_rate, -> > + ? ? ? .set_parent = _clk_ipg_per_set_parent, +> > + .parent = &lp_apm_clk, +> > + .get_rate = clk_ipg_per_get_rate, +> > + .set_parent = _clk_ipg_per_set_parent, > > +}; > > + > > +static struct clk uart_root_clk = { -> > + ? ? ? .parent = &pll2_sw_clk, -> > + ? ? ? .get_rate = clk_uart_get_rate, -> > + ? ? ? .set_parent = _clk_uart_set_parent, +> > + .parent = &pll2_sw_clk, +> > + .get_rate = clk_uart_get_rate, +> > + .set_parent = _clk_uart_set_parent, > > +}; > > + > > +static struct clk ahb_max_clk = { -> > + ? ? ? .parent = &ahb_clk, -> > + ? ? ? .enable_reg = MXC_CCM_CCGR0, -> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, -> > + ? ? ? .enable = _clk_max_enable, -> > + ? ? ? .disable = _clk_max_disable, +> > + .parent = &ahb_clk, +> > + .enable_reg = MXC_CCM_CCGR0, +> > + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, +> > + .enable = _clk_max_enable, +> > + .disable = _clk_max_disable, > > +}; > > + > > +static struct clk aips_tz1_clk = { -> > + ? ? ? .parent = &ahb_clk, -> > + ? ? ? .secondary = &ahb_max_clk, -> > + ? ? ? .enable_reg = MXC_CCM_CCGR0, -> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, -> > + ? ? ? .enable = _clk_ccgr_enable, -> > + ? ? ? .disable = _clk_ccgr_disable_inwait, +> > + .parent = &ahb_clk, +> > + .secondary = &ahb_max_clk, +> > + .enable_reg = MXC_CCM_CCGR0, +> > + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, +> > + .enable = _clk_ccgr_enable, +> > + .disable = _clk_ccgr_disable_inwait, > > +}; > > + > > +static struct clk aips_tz2_clk = { -> > + ? ? ? .parent = &ahb_clk, -> > + ? ? ? .secondary = &ahb_max_clk, -> > + ? ? ? .enable_reg = MXC_CCM_CCGR0, -> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, -> > + ? ? ? .enable = _clk_ccgr_enable, -> > + ? ? ? .disable = _clk_ccgr_disable_inwait, +> > + .parent = &ahb_clk, +> > + .secondary = &ahb_max_clk, +> > + .enable_reg = MXC_CCM_CCGR0, +> > + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, +> > + .enable = _clk_ccgr_enable, +> > + .disable = _clk_ccgr_disable_inwait, > > +}; > > + > > +static struct clk gpt_32k_clk = { -> > + ? ? ? .id = 0, -> > + ? ? ? .parent = &ckil_clk, +> > + .id = 0, +> > + .parent = &ckil_clk, > > +}; > > + -> > +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) ? ?\ -> > + ? ? ? static struct clk name = { ? ? ? ? ? ? ? ? ? ? ?\ -> > + ? ? ? ? ? ? ? .id ? ? ? ? ? ? = i, ? ? ? ? ? ? ? ? ? ?\ -> > + ? ? ? ? ? ? ? .enable_reg ? ? = er, ? ? ? ? ? ? ? ? ? \ -> > + ? ? ? ? ? ? ? .enable_shift ? = es, ? ? ? ? ? ? ? ? ? \ -> > + ? ? ? ? ? ? ? .get_rate ? ? ? = gr, ? ? ? ? ? ? ? ? ? \ -> > + ? ? ? ? ? ? ? .set_rate ? ? ? = sr, ? ? ? ? ? ? ? ? ? \ -> > + ? ? ? ? ? ? ? .enable ? ? ? ? = _clk_ccgr_enable, ? ? \ -> > + ? ? ? ? ? ? ? .disable ? ? ? ?= _clk_ccgr_disable, ? ?\ -> > + ? ? ? ? ? ? ? .parent ? ? ? ? = p, ? ? ? ? ? ? ? ? ? ?\ -> > + ? ? ? ? ? ? ? .secondary ? ? ?= s, ? ? ? ? ? ? ? ? ? ?\ -> > + ? ? ? } +> > +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ +> > + static struct clk name = { \ +> > + .id = i, \ +> > + .enable_reg = er, \ +> > + .enable_shift = es, \ +> > + .get_rate = gr, \ +> > + .set_rate = sr, \ +> > + .enable = _clk_ccgr_enable, \ +> > + .disable = _clk_ccgr_disable, \ +> > + .parent = p, \ +> > + .secondary = s, \ +> > + } > > + > > +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, -> > + ? get_rate, set_rate, parent, secondary); */ +> > + get_rate, set_rate, parent, secondary); */ > > + > > +/* Shared peripheral bus arbiter */ > > +DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL); +> > + NULL, NULL, &ipg_clk, NULL); > > + > > +/* UART */ > > +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, -> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL); +> > + NULL, NULL, &uart_root_clk, NULL); > > +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, -> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL); +> > + NULL, NULL, &uart_root_clk, NULL); > > +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, -> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL); +> > + NULL, NULL, &uart_root_clk, NULL); > > +DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, &aips_tz1_clk); +> > + NULL, NULL, &ipg_clk, &aips_tz1_clk); > > +DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, &aips_tz1_clk); +> > + NULL, NULL, &ipg_clk, &aips_tz1_clk); > > +DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, &spba_clk); +> > + NULL, NULL, &ipg_clk, &spba_clk); > > + > > +/* GPT */ > > +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_perclk, NULL); +> > + NULL, NULL, &ipg_perclk, NULL); > > +DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL); +> > + NULL, NULL, &ipg_clk, NULL); > > + > > +/* FEC */ > > +DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, -> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL); +> > + NULL, NULL, &ipg_clk, NULL); > > + > > +#define _REGISTER_CLOCK(d, n, c) \ -> > + ? ? ? { \ -> > + ? ? ? ? ? ? ? .dev_id = d, \ -> > + ? ? ? ? ? ? ? .con_id = n, \ -> > + ? ? ? ? ? ? ? .clk = &c, ? \ -> > + ? ? ? }, +> > + { \ +> > + .dev_id = d, \ +> > + .con_id = n, \ +> > + .clk = &c, \ +> > + }, > > + > > +static struct clk_lookup lookups[] __initdata = { -> > + ? ? ? _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) -> > + ? ? ? _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) -> > + ? ? ? _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) -> > + ? ? ? _REGISTER_CLOCK(NULL, "gpt", gpt_clk) -> > + ? ? ? _REGISTER_CLOCK("fec.0", NULL, fec_clk) +> > + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) +> > + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) +> > + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) +> > + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) +> > + _REGISTER_CLOCK("fec.0", NULL, fec_clk) > > +}; > > + > > +static void clk_tree_init(void) > > +{ -> > + ? ? ? u32 reg; -> > + -> > + ? ? ? ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); -> > + -> > + ? ? ? /* -> > + ? ? ? ?* Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at -> > + ? ? ? ?* 8MHz, its derived from lp_apm. -> > + ? ? ? ?* FIXME: Verify if true for all boards -> > + ? ? ? ?*/ -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR); -> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; -> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; -> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; -> > + ? ? ? reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); -> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR); -> > + -> > + ? ? ? /* set parent for pll1, pll2 and pll3 */ -> > + ? ? ? pll1_main_clk.parent = &osc_clk; -> > + ? ? ? pll2_sw_clk.parent = &osc_clk; -> > + ? ? ? pll3_sw_clk.parent = &osc_clk; -> > + -> > + ? ? ? /* set ipg_perclk parent */ -> > + ? ? ? ipg_perclk.parent = &lp_apm_clk; -> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR); -> > + ? ? ? if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { -> > + ? ? ? ? ? ? ? ipg_perclk.parent = &ipg_clk; -> > + ? ? ? } else { -> > + ? ? ? ? ? ? ? if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) -> > + ? ? ? ? ? ? ? ? ? ? ? ipg_perclk.parent = &main_bus_clk; -> > + ? ? ? } +> > + u32 reg; +> > + +> > + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); +> > + +> > + /* +> > + * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at +> > + * 8MHz, its derived from lp_apm. +> > + * FIXME: Verify if true for all boards +> > + */ +> > + reg = __raw_readl(MXC_CCM_CBCDR); +> > + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; +> > + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; +> > + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; +> > + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); +> > + __raw_writel(reg, MXC_CCM_CBCDR); +> > + +> > + /* set parent for pll1, pll2 and pll3 */ +> > + pll1_main_clk.parent = &osc_clk; +> > + pll2_sw_clk.parent = &osc_clk; +> > + pll3_sw_clk.parent = &osc_clk; +> > + +> > + /* set ipg_perclk parent */ +> > + ipg_perclk.parent = &lp_apm_clk; +> > + reg = __raw_readl(MXC_CCM_CBCMR); +> > + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { +> > + ipg_perclk.parent = &ipg_clk; +> > + } else { +> > + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) +> > + ipg_perclk.parent = &main_bus_clk; +> > + } > > +} > > + > > +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, -> > + ? ? ? ? ? ? ? ? ? ? ? unsigned long ckih1, unsigned long ckih2) +> > + unsigned long ckih1, unsigned long ckih2) > > +{ -> > + ? ? ? int i; +> > + int i; > > + -> > + ? ? ? external_low_reference = ckil; -> > + ? ? ? external_high_reference = ckih1; -> > + ? ? ? ckih2_reference = ckih2; -> > + ? ? ? oscillator_reference = osc; +> > + external_low_reference = ckil; +> > + external_high_reference = ckih1; +> > + ckih2_reference = ckih2; +> > + oscillator_reference = osc; > > + -> > + ? ? ? for (i = 0; i < ARRAY_SIZE(lookups); i++) -> > + ? ? ? ? ? ? ? clkdev_add(&lookups[i]); +> > + for (i = 0; i < ARRAY_SIZE(lookups); i++) +> > + clkdev_add(&lookups[i]); > > + -> > + ? ? ? clk_tree_init(); +> > + clk_tree_init(); > > + -> > + ? ? ? clk_enable(&cpu_clk); -> > + ? ? ? clk_enable(&main_bus_clk); +> > + clk_enable(&cpu_clk); +> > + clk_enable(&main_bus_clk); > > + -> > + ? ? ? /* System timer */ -> > + ? ? ? mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), -> > + ? ? ? ? ? ? ? MX51_MXC_INT_GPT); -> > + ? ? ? return 0; +> > + /* System timer */ +> > + mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), +> > + MX51_MXC_INT_GPT); +> > + return 0; > > +} > > diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c > > new file mode 100644 @@ -963,27 +963,27 @@ Heh, yes :) > > + > > +static int __init post_cpu_init(void) > > +{ -> > + ? ? ? unsigned int reg; -> > + ? ? ? void __iomem *base; -> > + -> > + ? ? ? if (cpu_is_mx51()) { -> > + ? ? ? ? ? ? ? base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x40); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x44); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x48); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x4C); -> > + ? ? ? ? ? ? ? reg = __raw_readl(base + 0x50) & 0x00FFFFFF; -> > + ? ? ? ? ? ? ? __raw_writel(reg, base + 0x50); -> > + -> > + ? ? ? ? ? ? ? base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x40); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x44); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x48); -> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x4C); -> > + ? ? ? ? ? ? ? reg = __raw_readl(base + 0x50) & 0x00FFFFFF; -> > + ? ? ? ? ? ? ? __raw_writel(reg, base + 0x50); -> > + ? ? ? } -> > + ? ? ? return 0; +> > + unsigned int reg; +> > + void __iomem *base; +> > + +> > + if (cpu_is_mx51()) { +> > + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); +> > + __raw_writel(0x0, base + 0x40); +> > + __raw_writel(0x0, base + 0x44); +> > + __raw_writel(0x0, base + 0x48); +> > + __raw_writel(0x0, base + 0x4C); +> > + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; +> > + __raw_writel(reg, base + 0x50); +> > + +> > + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); +> > + __raw_writel(0x0, base + 0x40); +> > + __raw_writel(0x0, base + 0x44); +> > + __raw_writel(0x0, base + 0x48); +> > + __raw_writel(0x0, base + 0x4C); +> > + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; +> > + __raw_writel(reg, base + 0x50); +> > + } +> > + return 0; > > +} > > + > > +postcore_initcall(post_cpu_init); @@ -1006,16 +1006,16 @@ Heh, yes :) > > +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ > > +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ > > + -> > +#define MX51_CCM_BASE ? ? ? ? ?MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) -> > +#define MX51_DPLL1_BASE ? ? ? ? ? ? ? ?MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) -> > +#define MX51_DPLL2_BASE ? ? ? ? ? ? ? ?MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) +> > +#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) +> > +#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) +> > +#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) > > .... skipping register definitions .... > -> > +#define MXC_SRPGC_EMI_PUPSCR ? (MXC_SRPGC_EMI_BASE + 0x4) -> > +#define MXC_SRPGC_EMI_PDNSCR ? (MXC_SRPGC_EMI_BASE + 0x8) +> > +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +> > +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) > > + -> > +#endif ? ? ? ? ? ? ? ? ? ? ? ? /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ +> > +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ > > diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c > > new file mode 100644 > > index 0000000..55eb089 @@ -1038,85 +1038,85 @@ Heh, yes :) > > +#include <mach/imx-uart.h> > > + > > +static struct resource uart0[] = { -> > + ? ? ? { -> > + ? ? ? ? ? ? ? .start = MX51_UART1_BASE_ADDR, -> > + ? ? ? ? ? ? ? .end = MX51_UART1_BASE_ADDR + 0x0B5, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM, -> > + ? ? ? }, { -> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART1, -> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART1, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ, -> > + ? ? ? }, +> > + { +> > + .start = MX51_UART1_BASE_ADDR, +> > + .end = MX51_UART1_BASE_ADDR + 0x0B5, +> > + .flags = IORESOURCE_MEM, +> > + }, { +> > + .start = MX51_MXC_INT_UART1, +> > + .end = MX51_MXC_INT_UART1, +> > + .flags = IORESOURCE_IRQ, +> > + }, > > +}; > > + > > +struct platform_device mxc_uart_device0 = { -> > + ? ? ? .name = "imx-uart", -> > + ? ? ? .id = 0, -> > + ? ? ? .resource = uart0, -> > + ? ? ? .num_resources = ARRAY_SIZE(uart0), +> > + .name = "imx-uart", +> > + .id = 0, +> > + .resource = uart0, +> > + .num_resources = ARRAY_SIZE(uart0), > > +}; > > + > > +static struct resource uart1[] = { -> > + ? ? ? { -> > + ? ? ? ? ? ? ? .start = MX51_UART2_BASE_ADDR, -> > + ? ? ? ? ? ? ? .end = MX51_UART2_BASE_ADDR + 0x0B5, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM, -> > + ? ? ? }, { -> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART2, -> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART2, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ, -> > + ? ? ? }, +> > + { +> > + .start = MX51_UART2_BASE_ADDR, +> > + .end = MX51_UART2_BASE_ADDR + 0x0B5, +> > + .flags = IORESOURCE_MEM, +> > + }, { +> > + .start = MX51_MXC_INT_UART2, +> > + .end = MX51_MXC_INT_UART2, +> > + .flags = IORESOURCE_IRQ, +> > + }, > > +}; > > + > > +struct platform_device mxc_uart_device1 = { -> > + ? ? ? .name = "imx-uart", -> > + ? ? ? .id = 1, -> > + ? ? ? .resource = uart1, -> > + ? ? ? .num_resources = ARRAY_SIZE(uart1), +> > + .name = "imx-uart", +> > + .id = 1, +> > + .resource = uart1, +> > + .num_resources = ARRAY_SIZE(uart1), > > +}; > > + > > +static struct resource uart2[] = { -> > + ? ? ? { -> > + ? ? ? ? ? ? ? .start = MX51_UART3_BASE_ADDR, -> > + ? ? ? ? ? ? ? .end = MX51_UART3_BASE_ADDR + 0x0B5, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM, -> > + ? ? ? }, { -> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART3, -> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART3, -> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ, -> > + ? ? ? }, +> > + { +> > + .start = MX51_UART3_BASE_ADDR, +> > + .end = MX51_UART3_BASE_ADDR + 0x0B5, +> > + .flags = IORESOURCE_MEM, +> > + }, { +> > + .start = MX51_MXC_INT_UART3, +> > + .end = MX51_MXC_INT_UART3, +> > + .flags = IORESOURCE_IRQ, +> > + }, > > +}; > > + > > +struct platform_device mxc_uart_device2 = { -> > + ? ? ? .name = "imx-uart", -> > + ? ? ? .id = 2, -> > + ? ? ? .resource = uart2, -> > + ? ? ? .num_resources = ARRAY_SIZE(uart2), +> > + .name = "imx-uart", +> > + .id = 2, +> > + .resource = uart2, +> > + .num_resources = ARRAY_SIZE(uart2), > > +}; > > + > > +static struct resource mxc_fec_resources[] = { -> > + ? ? ? { -> > + ? ? ? ? ? ? ? .start ?= MX51_MXC_FEC_BASE_ADDR, -> > + ? ? ? ? ? ? ? .end ? ?= MX51_MXC_FEC_BASE_ADDR + 0xfff, -> > + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM, -> > + ? ? ? }, { -> > + ? ? ? ? ? ? ? .start ?= MX51_MXC_INT_FEC, -> > + ? ? ? ? ? ? ? .end ? ?= MX51_MXC_INT_FEC, -> > + ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ, -> > + ? ? ? }, +> > + { +> > + .start = MX51_MXC_FEC_BASE_ADDR, +> > + .end = MX51_MXC_FEC_BASE_ADDR + 0xfff, +> > + .flags = IORESOURCE_MEM, +> > + }, { +> > + .start = MX51_MXC_INT_FEC, +> > + .end = MX51_MXC_INT_FEC, +> > + .flags = IORESOURCE_IRQ, +> > + }, > > +}; > > + > > +struct platform_device mxc_fec_device = { -> > + ? ? ? .name = "fec", -> > + ? ? ? .id = 0, -> > + ? ? ? .num_resources = ARRAY_SIZE(mxc_fec_resources), -> > + ? ? ? .resource = mxc_fec_resources, +> > + .name = "fec", +> > + .id = 0, +> > + .num_resources = ARRAY_SIZE(mxc_fec_resources), +> > + .resource = mxc_fec_resources, > > +}; > > + > > +/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ > > +int __init mxc_register_gpios(void) > > +{ -> > + ? ? ? return 0; +> > + return 0; > > +} > > diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h > > new file mode 100644 @@ -1138,7 +1138,7 @@ Heh, yes :) > > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. > > + * > > + * The code contained herein is licensed under the GNU General Public -> > + * License. ?You may obtain a copy of the GNU General Public License +> > + * License. You may obtain a copy of the GNU General Public License > > + * Version 2 or later at the following locations: > > + * > > + * http://www.opensource.org/licenses/gpl-license.html @@ -1160,41 +1160,41 @@ Heh, yes :) > > + * Define the MX51 memory map. > > + */ > > +static struct map_desc mxc_io_desc[] __initdata = { -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_IRAM_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), -> > + ? ? ? ?.length = MX51_IRAM_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_DEBUG_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), -> > + ? ? ? ?.length = MX51_DEBUG_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_TZIC_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR), -> > + ? ? ? ?.length = MX51_TZIC_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_AIPS1_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), -> > + ? ? ? ?.length = MX51_AIPS1_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_SPBA0_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), -> > + ? ? ? ?.length = MX51_SPBA0_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_AIPS2_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), -> > + ? ? ? ?.length = MX51_AIPS2_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, -> > + ? ? ? { -> > + ? ? ? ?.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT, -> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR), -> > + ? ? ? ?.length = MX51_NFC_AXI_SIZE, -> > + ? ? ? ?.type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_IRAM_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), +> > + .length = MX51_IRAM_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_DEBUG_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), +> > + .length = MX51_DEBUG_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_TZIC_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR), +> > + .length = MX51_TZIC_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_AIPS1_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), +> > + .length = MX51_AIPS1_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_SPBA0_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), +> > + .length = MX51_SPBA0_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_AIPS2_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), +> > + .length = MX51_AIPS2_SIZE, +> > + .type = MT_DEVICE}, +> > + { +> > + .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT, +> > + .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR), +> > + .length = MX51_NFC_AXI_SIZE, +> > + .type = MT_DEVICE}, > > Weird alignment, guess due to leading white spaces? @@ -1208,5 +1208,5 @@ Thanks for the review. /Amit -- ---------------------------------------------------------------------- -Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com +Amit Kucheria, Kernel Engineer || amit.kucheria@canonical.com ---------------------------------------------------------------------- diff --git a/a/content_digest b/N1/content_digest index 01e33d0..8727f74 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,10 +6,20 @@ "ref\0ec63e5978fd5ac5d308ede5916e648ba925818eb.1265173480.git.amit.kucheria@canonical.com\0" "ref\0f10f79e7313ecdeeb59ab881795baedf2430c636.1265173480.git.amit.kucheria@canonical.com\0" "ref\0f17812d71002022303m2fb0ba5cmb6cdac6bccbadde6@mail.gmail.com\0" - "From\0amit.kucheria@canonical.com (Amit Kucheria)\0" - "Subject\0[PATCHv2 05/11] mxc: Core support for i.MX5 series of processors from Freescale\0" + "From\0Amit Kucheria <amit.kucheria@canonical.com>\0" + "Subject\0Re: [PATCHv2 05/11] mxc: Core support for i.MX5 series of processors from Freescale\0" "Date\0Wed, 3 Feb 2010 06:20:15 -0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Eric Miao <eric.y.miao@gmail.com>\0" + "Cc\0List Linux Kernel <linux-kernel@vger.kernel.org>" + linux@arm.linux.org.uk + Dinh.Nguyen@freescale.com + s.hauer@pengutronix.de + grant.likely@secretlab.ca + r.herring@freescale.com + linux-arm-kernel@lists.infradead.org + daniel@caiaq.de + bryan.wu@canonical.com + " valentin.longchamp@epfl.ch\0" "\00:1\0" "b\0" "On 10 Feb 02, Eric Miao wrote:\n" @@ -21,25 +31,25 @@ "> >\n" "> > Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>\n" "> > ---\n" - "> > ?arch/arm/mach-mx5/clock.c ? ? ? ? ? ? ? ? ? ?| ?848 ++++++++++++++++++++++++++\n" - "> > ?arch/arm/mach-mx5/cpu.c ? ? ? ? ? ? ? ? ? ? ?| ? 45 ++\n" - "> > ?arch/arm/mach-mx5/crm_regs.h ? ? ? ? ? ? ? ? | ?583 ++++++++++++++++++\n" - "> > ?arch/arm/mach-mx5/devices.c ? ? ? ? ? ? ? ? ?| ? 96 +++\n" - "> > ?arch/arm/mach-mx5/devices.h ? ? ? ? ? ? ? ? ?| ? ?4 +\n" - "> > ?arch/arm/mach-mx5/mm.c ? ? ? ? ? ? ? ? ? ? ? | ? 88 +++\n" - "> > ?arch/arm/plat-mxc/include/mach/common.h ? ? ?| ? ?1 +\n" - "> > ?arch/arm/plat-mxc/include/mach/debug-macro.S | ? ?4 +-\n" - "> > ?arch/arm/plat-mxc/include/mach/iomux-mx51.h ?| ?340 +++++++++++\n" - "> > ?arch/arm/plat-mxc/include/mach/mx51.h ? ? ? ?| ?454 ++++++++++++++\n" - "> > ?10 files changed, 2461 insertions(+), 2 deletions(-)\n" - "> > ?create mode 100644 arch/arm/mach-mx5/clock.c\n" - "> > ?create mode 100644 arch/arm/mach-mx5/cpu.c\n" - "> > ?create mode 100644 arch/arm/mach-mx5/crm_regs.h\n" - "> > ?create mode 100644 arch/arm/mach-mx5/devices.c\n" - "> > ?create mode 100644 arch/arm/mach-mx5/devices.h\n" - "> > ?create mode 100644 arch/arm/mach-mx5/mm.c\n" - "> > ?create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h\n" - "> > ?create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h\n" + "> > \302\240arch/arm/mach-mx5/clock.c \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240| \302\240848 ++++++++++++++++++++++++++\n" + "> > \302\240arch/arm/mach-mx5/cpu.c \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240| \302\240 45 ++\n" + "> > \302\240arch/arm/mach-mx5/crm_regs.h \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 | \302\240583 ++++++++++++++++++\n" + "> > \302\240arch/arm/mach-mx5/devices.c \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240| \302\240 96 +++\n" + "> > \302\240arch/arm/mach-mx5/devices.h \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240| \302\240 \302\2404 +\n" + "> > \302\240arch/arm/mach-mx5/mm.c \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 | \302\240 88 +++\n" + "> > \302\240arch/arm/plat-mxc/include/mach/common.h \302\240 \302\240 \302\240| \302\240 \302\2401 +\n" + "> > \302\240arch/arm/plat-mxc/include/mach/debug-macro.S | \302\240 \302\2404 +-\n" + "> > \302\240arch/arm/plat-mxc/include/mach/iomux-mx51.h \302\240| \302\240340 +++++++++++\n" + "> > \302\240arch/arm/plat-mxc/include/mach/mx51.h \302\240 \302\240 \302\240 \302\240| \302\240454 ++++++++++++++\n" + "> > \302\24010 files changed, 2461 insertions(+), 2 deletions(-)\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/clock.c\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/cpu.c\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/crm_regs.h\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/devices.c\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/devices.h\n" + "> > \302\240create mode 100644 arch/arm/mach-mx5/mm.c\n" + "> > \302\240create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51.h\n" + "> > \302\240create mode 100644 arch/arm/plat-mxc/include/mach/mx51.h\n" "> >\n" "> > diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c\n" "> > new file mode 100644\n" @@ -73,9 +83,9 @@ "> > +#include \"crm_regs.h\"\n" "> > +\n" "> > +static void __iomem *pll_base[] = {\n" - "> > + ? ? ? MX51_DPLL1_BASE,\n" - "> > + ? ? ? MX51_DPLL2_BASE,\n" - "> > + ? ? ? MX51_DPLL3_BASE,\n" + "> > + \302\240 \302\240 \302\240 MX51_DPLL1_BASE,\n" + "> > + \302\240 \302\240 \302\240 MX51_DPLL2_BASE,\n" + "> > + \302\240 \302\240 \302\240 MX51_DPLL3_BASE,\n" "> > +};\n" "> > +\n" "> > +/* External clock values passed-in by the board code */\n" @@ -92,184 +102,184 @@ "> > +static struct clk ahb_clk;\n" "> > +static struct clk ipg_clk;\n" "> > +\n" - "> > +#define MAX_DPLL_WAIT_TRIES ? ?1000 /* 1000 * udelay(1) = 1ms */\n" + "> > +#define MAX_DPLL_WAIT_TRIES \302\240 \302\2401000 /* 1000 * udelay(1) = 1ms */\n" "> > +\n" "> > +static int _clk_ccgr_enable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(clk->enable_reg);\n" - "> > + ? ? ? reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;\n" - "> > + ? ? ? __raw_writel(reg, clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, clk->enable_reg);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static void _clk_ccgr_disable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" - "> > + ? ? ? reg = __raw_readl(clk->enable_reg);\n" - "> > + ? ? ? reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);\n" - "> > + ? ? ? __raw_writel(reg, clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, clk->enable_reg);\n" "> > +\n" "> > +}\n" "> > +\n" "> > +static void _clk_ccgr_disable_inwait(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(clk->enable_reg);\n" - "> > + ? ? ? reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);\n" - "> > + ? ? ? reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;\n" - "> > + ? ? ? __raw_writel(reg, clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(clk->enable_reg);\n" + "> > + \302\240 \302\240 \302\240 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);\n" + "> > + \302\240 \302\240 \302\240 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, clk->enable_reg);\n" "> > +}\n" "> > +\n" "> > +/*\n" "> > + * For the 4-to-1 muxed input clock\n" "> > + */\n" "> > +static inline u32 _get_mux(struct clk *parent, struct clk *m0,\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ?struct clk *m1, struct clk *m2, struct clk *m3)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240struct clk *m1, struct clk *m2, struct clk *m3)\n" "> > +{\n" - "> > + ? ? ? if (parent == m0)\n" - "> > + ? ? ? ? ? ? ? return 0;\n" - "> > + ? ? ? else if (parent == m1)\n" - "> > + ? ? ? ? ? ? ? return 1;\n" - "> > + ? ? ? else if (parent == m2)\n" - "> > + ? ? ? ? ? ? ? return 2;\n" - "> > + ? ? ? else if (parent == m3)\n" - "> > + ? ? ? ? ? ? ? return 3;\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? BUG();\n" - "> > +\n" - "> > + ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == m0)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return 0;\n" + "> > + \302\240 \302\240 \302\240 else if (parent == m1)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return 1;\n" + "> > + \302\240 \302\240 \302\240 else if (parent == m2)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return 2;\n" + "> > + \302\240 \302\240 \302\240 else if (parent == m3)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return 3;\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 BUG();\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 return -EINVAL;\n" "> > +}\n" "> > +\n" "> > +static inline void __iomem *_get_pll_base(struct clk *pll)\n" "> > +{\n" - "> > + ? ? ? if (pll == &pll1_main_clk)\n" - "> > + ? ? ? ? ? ? ? return pll_base[0];\n" - "> > + ? ? ? else if (pll == &pll2_sw_clk)\n" - "> > + ? ? ? ? ? ? ? return pll_base[1];\n" - "> > + ? ? ? else if (pll == &pll3_sw_clk)\n" - "> > + ? ? ? ? ? ? ? return pll_base[2];\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? BUG();\n" - "> > +\n" - "> > + ? ? ? return NULL;\n" + "> > + \302\240 \302\240 \302\240 if (pll == &pll1_main_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return pll_base[0];\n" + "> > + \302\240 \302\240 \302\240 else if (pll == &pll2_sw_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return pll_base[1];\n" + "> > + \302\240 \302\240 \302\240 else if (pll == &pll3_sw_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return pll_base[2];\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 BUG();\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 return NULL;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_pll_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;\n" - "> > + ? ? ? unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;\n" - "> > + ? ? ? void __iomem *pllbase;\n" - "> > + ? ? ? s64 temp;\n" - "> > + ? ? ? unsigned long parent_rate;\n" - "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > +\n" - "> > + ? ? ? pllbase = _get_pll_base(clk);\n" - "> > +\n" - "> > + ? ? ? dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);\n" - "> > + ? ? ? pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;\n" - "> > + ? ? ? dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;\n" - "> > +\n" - "> > + ? ? ? if (pll_hfsm == 0) {\n" - "> > + ? ? ? ? ? ? ? dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);\n" - "> > + ? ? ? ? ? ? ? dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);\n" - "> > + ? ? ? ? ? ? ? dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);\n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);\n" - "> > + ? ? ? ? ? ? ? dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);\n" - "> > + ? ? ? ? ? ? ? dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);\n" - "> > + ? ? ? }\n" - "> > + ? ? ? pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;\n" - "> > + ? ? ? mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;\n" - "> > + ? ? ? mfi = (mfi <= 5) ? 5 : mfi;\n" - "> > + ? ? ? mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;\n" - "> > + ? ? ? mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;\n" - "> > + ? ? ? /* Sign extend to 32-bits */\n" - "> > + ? ? ? if (mfn >= 0x04000000) {\n" - "> > + ? ? ? ? ? ? ? mfn |= 0xFC000000;\n" - "> > + ? ? ? ? ? ? ? mfn_abs = -mfn;\n" - "> > + ? ? ? }\n" - "> > +\n" - "> > + ? ? ? ref_clk = 2 * parent_rate;\n" - "> > + ? ? ? if (dbl != 0)\n" - "> > + ? ? ? ? ? ? ? ref_clk *= 2;\n" - "> > +\n" - "> > + ? ? ? ref_clk /= (pdf + 1);\n" - "> > + ? ? ? temp = (u64) ref_clk * mfn_abs;\n" - "> > + ? ? ? do_div(temp, mfd + 1);\n" - "> > + ? ? ? if (mfn < 0)\n" - "> > + ? ? ? ? ? ? ? temp = -temp;\n" - "> > + ? ? ? temp = (ref_clk * mfi) + temp;\n" - "> > +\n" - "> > + ? ? ? return temp;\n" + "> > + \302\240 \302\240 \302\240 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;\n" + "> > + \302\240 \302\240 \302\240 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;\n" + "> > + \302\240 \302\240 \302\240 void __iomem *pllbase;\n" + "> > + \302\240 \302\240 \302\240 s64 temp;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 pllbase = _get_pll_base(clk);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);\n" + "> > + \302\240 \302\240 \302\240 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;\n" + "> > + \302\240 \302\240 \302\240 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 if (pll_hfsm == 0) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;\n" + "> > + \302\240 \302\240 \302\240 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;\n" + "> > + \302\240 \302\240 \302\240 mfi = (mfi <= 5) ? 5 : mfi;\n" + "> > + \302\240 \302\240 \302\240 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;\n" + "> > + \302\240 \302\240 \302\240 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;\n" + "> > + \302\240 \302\240 \302\240 /* Sign extend to 32-bits */\n" + "> > + \302\240 \302\240 \302\240 if (mfn >= 0x04000000) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mfn |= 0xFC000000;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mfn_abs = -mfn;\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 ref_clk = 2 * parent_rate;\n" + "> > + \302\240 \302\240 \302\240 if (dbl != 0)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ref_clk *= 2;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 ref_clk /= (pdf + 1);\n" + "> > + \302\240 \302\240 \302\240 temp = (u64) ref_clk * mfn_abs;\n" + "> > + \302\240 \302\240 \302\240 do_div(temp, mfd + 1);\n" + "> > + \302\240 \302\240 \302\240 if (mfn < 0)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 temp = -temp;\n" + "> > + \302\240 \302\240 \302\240 temp = (ref_clk * mfi) + temp;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 return temp;\n" "> > +}\n" "> > +\n" "> > +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" - "> > + ? ? ? void __iomem *pllbase;\n" - "> > +\n" - "> > + ? ? ? long mfi, pdf, mfn, mfd = 999999;\n" - "> > + ? ? ? s64 temp64;\n" - "> > + ? ? ? unsigned long quad_parent_rate;\n" - "> > + ? ? ? unsigned long pll_hfsm, dp_ctl;\n" - "> > + ? ? ? unsigned long parent_rate;\n" - "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > +\n" - "> > + ? ? ? pllbase = _get_pll_base(clk);\n" - "> > +\n" - "> > + ? ? ? quad_parent_rate = 4 * parent_rate;\n" - "> > + ? ? ? pdf = mfi = -1;\n" - "> > + ? ? ? while (++pdf < 16 && mfi < 5)\n" - "> > + ? ? ? ? ? ? ? mfi = rate * (pdf+1) / quad_parent_rate;\n" - "> > + ? ? ? if (mfi > 15)\n" - "> > + ? ? ? ? ? ? ? return -1;\n" - "> > + ? ? ? pdf--;\n" - "> > +\n" - "> > + ? ? ? temp64 = rate * (pdf+1) - quad_parent_rate * mfi;\n" - "> > + ? ? ? do_div(temp64, quad_parent_rate/1000000);\n" - "> > + ? ? ? mfn = (long)temp64;\n" - "> > +\n" - "> > + ? ? ? dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);\n" - "> > + ? ? ? /* use dpdck0_2 */\n" - "> > + ? ? ? __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);\n" - "> > + ? ? ? pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;\n" - "> > + ? ? ? if (pll_hfsm == 0) {\n" - "> > + ? ? ? ? ? ? ? reg = mfi << 4 | pdf;\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_OP);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);\n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? reg = mfi << 4 | pdf;\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);\n" - "> > + ? ? ? }\n" - "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" + "> > + \302\240 \302\240 \302\240 void __iomem *pllbase;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 long mfi, pdf, mfn, mfd = 999999;\n" + "> > + \302\240 \302\240 \302\240 s64 temp64;\n" + "> > + \302\240 \302\240 \302\240 unsigned long quad_parent_rate;\n" + "> > + \302\240 \302\240 \302\240 unsigned long pll_hfsm, dp_ctl;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 pllbase = _get_pll_base(clk);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 quad_parent_rate = 4 * parent_rate;\n" + "> > + \302\240 \302\240 \302\240 pdf = mfi = -1;\n" + "> > + \302\240 \302\240 \302\240 while (++pdf < 16 && mfi < 5)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mfi = rate * (pdf+1) / quad_parent_rate;\n" + "> > + \302\240 \302\240 \302\240 if (mfi > 15)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -1;\n" + "> > + \302\240 \302\240 \302\240 pdf--;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;\n" + "> > + \302\240 \302\240 \302\240 do_div(temp64, quad_parent_rate/1000000);\n" + "> > + \302\240 \302\240 \302\240 mfn = (long)temp64;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);\n" + "> > + \302\240 \302\240 \302\240 /* use dpdck0_2 */\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);\n" + "> > + \302\240 \302\240 \302\240 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;\n" + "> > + \302\240 \302\240 \302\240 if (pll_hfsm == 0) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = mfi << 4 | pdf;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = mfi << 4 | pdf;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static int _clk_pll_enable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" - "> > + ? ? ? void __iomem *pllbase;\n" - "> > + ? ? ? int i = 0;\n" - "> > +\n" - "> > + ? ? ? pllbase = _get_pll_base(clk);\n" - "> > + ? ? ? reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;\n" - "> > + ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);\n" - "> > +\n" - "> > + ? ? ? /* Wait for lock */\n" - "> > + ? ? ? while ((!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF))\n" - "> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? i++;\n" - "> > + ? ? ? ? ? ? ? udelay(1);\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" + "> > + \302\240 \302\240 \302\240 void __iomem *pllbase;\n" + "> > + \302\240 \302\240 \302\240 int i = 0;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 pllbase = _get_pll_base(clk);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 /* Wait for lock */\n" + "> > + \302\240 \302\240 \302\240 while ((!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF))\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 && i < MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 i++;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 udelay(1);\n" + "> > + \302\240 \302\240 \302\240 }\n" "> \n" "> \n" "> Mmm... this really hurts my eyes:\n" @@ -286,65 +296,65 @@ "(Shrug) I picked it up from OMAP code. But your style is better.\n" "\n" "> > +\n" - "> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? printk(KERN_ERR \"MX5: pll locking failed\\n\");\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 if (i == MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_ERR \"MX5: pll locking failed\\n\");\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static void _clk_pll_disable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" - "> > + ? ? ? void __iomem *pllbase;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" + "> > + \302\240 \302\240 \302\240 void __iomem *pllbase;\n" "> > +\n" - "> > + ? ? ? pllbase = _get_pll_base(clk);\n" - "> > + ? ? ? reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;\n" - "> > + ? ? ? __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);\n" + "> > + \302\240 \302\240 \302\240 pllbase = _get_pll_base(clk);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);\n" "> > +}\n" "> > +\n" "> > +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR);\n" "> > +\n" - "> > + ? ? ? /* When switching from pll_main_clk to a bypass clock, first select a\n" - "> > + ? ? ? ? ?multiplexed clock in 'step_sel', then shift the glitchless mux\n" - "> > + ? ? ? ? ?'pll1_sw_clk_sel'.\n" - "> > + ? ? ? ? ?When switching back, do it in reverse order\n" - "> > + ? ? ? */\n" + "> > + \302\240 \302\240 \302\240 /* When switching from pll_main_clk to a bypass clock, first select a\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240multiplexed clock in 'step_sel', then shift the glitchless mux\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240'pll1_sw_clk_sel'.\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240When switching back, do it in reverse order\n" + "> > + \302\240 \302\240 \302\240 */\n" "> \n" "> comment style ... not sure if this leaks apw's checkscripts, heh :)\n" "\n" "The patch was checkpatch approved ;)\n" "But will fix.\n" "\n" - "> > + ? ? ? if (parent == &pll1_main_clk) {\n" - "> > + ? ? ? ? ? ? ? /* Switch to pll1_main_clk */\n" - "> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, MXC_CCM_CCSR);\n" - "> > + ? ? ? ? ? ? ? /* step_clk mux switched to lp_apm, to save power. */\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR);\n" - "> > + ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_LP_APM <<\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? if (parent == &lp_apm_clk) {\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_LP_APM <<\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" - "> > + ? ? ? ? ? ? ? } else ?if (parent == &pll2_sw_clk) {\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED <<\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" - "> > + ? ? ? ? ? ? ? } else ?if (parent == &pll3_sw_clk) {\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED <<\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" - "> > + ? ? ? ? ? ? ? } else\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == &pll1_main_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* Switch to pll1_main_clk */\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* step_clk mux switched to lp_apm, to save power. */\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (MXC_CCM_CCSR_STEP_SEL_LP_APM <<\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 if (parent == &lp_apm_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (MXC_CCM_CCSR_STEP_SEL_LP_APM <<\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 } else \302\240if (parent == &pll2_sw_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED <<\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 } else \302\240if (parent == &pll3_sw_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 (MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED <<\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CCSR_STEP_SEL_OFFSET);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 } else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" "> \n" "> Again, hurts my eyes:\n" "> \n" @@ -362,168 +372,168 @@ "Fixed.\n" "\n" "> > +\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, MXC_CCM_CCSR);\n" - "> > + ? ? ? ? ? ? ? /* Switch to step_clk */\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR);\n" - "> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;\n" - "> > + ? ? ? }\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR);\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* Switch to step_clk */\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_pll1_sw_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg, div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" - "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > +\n" - "> > + ? ? ? div = 1;\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR);\n" - "> > +\n" - "> > + ? ? ? if (clk->parent == &pll2_sw_clk) {\n" - "> > + ? ? ? ? ? ? ? div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;\n" - "> > + ? ? ? } else if (clk->parent == &pll3_sw_clk) {\n" - "> > + ? ? ? ? ? ? ? div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;\n" - "> > + ? ? ? }\n" - "> > + ? ? ? return parent_rate / div;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 div = 1;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 if (clk->parent == &pll2_sw_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 } else if (clk->parent == &pll3_sw_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / div;\n" "> > +}\n" "> > +\n" "> > +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR);\n" "> > +\n" - "> > + ? ? ? if (parent == &pll2_sw_clk)\n" - "> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == &pll2_sw_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;\n" "> > +\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR);\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? if (parent == &osc_clk)\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == &osc_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" "> > +\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CCSR);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CCSR);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_arm_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 cacrr, div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 cacrr, div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > + ? ? ? cacrr = __raw_readl(MXC_CCM_CACRR);\n" - "> > + ? ? ? div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 cacrr = __raw_readl(MXC_CCM_CACRR);\n" + "> > + \302\240 \302\240 \302\240 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;\n" "> > +\n" - "> > + ? ? ? return parent_rate / div;\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / div;\n" "> > +}\n" "> > +\n" "> > +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg, mux;\n" - "> > + ? ? ? int i = 0;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, mux;\n" + "> > + \302\240 \302\240 \302\240 int i = 0;\n" "> > +\n" - "> > + ? ? ? mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;\n" - "> > + ? ? ? reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCMR);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CBCMR);\n" "> > +\n" - "> > + ? ? ? /* Wait for lock */\n" - "> > + ? ? ? while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)\n" - "> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? i++;\n" - "> > + ? ? ? ? ? ? ? udelay(1);\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 /* Wait for lock */\n" + "> > + \302\240 \302\240 \302\240 while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 && i < MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 i++;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 udelay(1);\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" - "> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? printk(KERN_ERR \"MX5: Set parent for periph_apm clock failed\\n\");\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 if (i == MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_ERR \"MX5: Set parent for periph_apm clock failed\\n\");\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_main_bus_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? return clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 return clk_get_rate(clk->parent);\n" "> > +}\n" "> > +\n" "> > +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" "> > +\n" - "> > + ? ? ? if (parent == &pll2_sw_clk)\n" - "> > + ? ? ? ? ? ? ? reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;\n" - "> > + ? ? ? else if (parent == &periph_apm_clk)\n" - "> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;\n" - "> > + ? ? ? else\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == &pll2_sw_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 else if (parent == &periph_apm_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 else\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" "> > +\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CBCDR);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static struct clk main_bus_clk = {\n" - "> > + ? ? ? .parent = &pll2_sw_clk,\n" - "> > + ? ? ? .set_parent = _clk_main_bus_set_parent,\n" - "> > + ? ? ? .get_rate = clk_main_bus_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .parent = &pll2_sw_clk,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_main_bus_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_main_bus_get_rate,\n" "> > +};\n" "> > +\n" "> > +static unsigned long clk_ahb_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg, div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" - "> > + ? ? ? div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ?MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;\n" - "> > + ? ? ? return parent_rate / div;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / div;\n" "> > +}\n" "> > +\n" "> > +\n" "> > +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)\n" "> > +{\n" - "> > + ? ? ? u32 reg, div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" - "> > + ? ? ? int i = 0;\n" - "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > +\n" - "> > + ? ? ? div = parent_rate / rate;\n" - "> > + ? ? ? if (div > 8 || div < 1 || ((parent_rate / div) != rate))\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" - "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;\n" - "> > + ? ? ? reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR);\n" - "> > +\n" - "> > + ? ? ? /* Wait for lock */\n" - "> > + ? ? ? while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY)\n" - "> > + ? ? ? ? ? ? ? && i < MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? i++;\n" - "> > + ? ? ? ? ? ? ? udelay(1);\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 u32 reg, div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 int i = 0;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 div = parent_rate / rate;\n" + "> > + \302\240 \302\240 \302\240 if (div > 8 || div < 1 || ((parent_rate / div) != rate))\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CBCDR);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 /* Wait for lock */\n" + "> > + \302\240 \302\240 \302\240 while ((__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 && i < MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 i++;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 udelay(1);\n" + "> > + \302\240 \302\240 \302\240 }\n" "> \n" "> Provided this loop sequence appears so many times here, maybe we can just\n" "> invent a static inline function for this, e.g. dpll_wait_flags(register, flags)\n" @@ -531,187 +541,187 @@ "Will investigate.\n" "\n" "> > +\n" - "> > + ? ? ? if (i == MAX_DPLL_WAIT_TRIES) {\n" - "> > + ? ? ? ? ? ? ? printk(KERN_ERR \"MX5: clk_ahb_set_rate failed\\n\");\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 if (i == MAX_DPLL_WAIT_TRIES) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 printk(KERN_ERR \"MX5: clk_ahb_set_rate failed\\n\");\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long _clk_ahb_round_rate(struct clk *clk,\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long rate)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 unsigned long rate)\n" "> > +{\n" - "> > + ? ? ? u32 div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" "> > +\n" - "> > + ? ? ? div = parent_rate / rate;\n" - "> > + ? ? ? if (div > 8)\n" - "> > + ? ? ? ? ? ? ? div = 8;\n" - "> > + ? ? ? else if (div == 0)\n" - "> > + ? ? ? ? ? ? ? div++;\n" - "> > + ? ? ? return parent_rate / div;\n" + "> > + \302\240 \302\240 \302\240 div = parent_rate / rate;\n" + "> > + \302\240 \302\240 \302\240 if (div > 8)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 div = 8;\n" + "> > + \302\240 \302\240 \302\240 else if (div == 0)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 div++;\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / div;\n" "> > +}\n" "> > +\n" "> > +\n" "> > +static int _clk_max_enable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? _clk_ccgr_enable(clk);\n" + "> > + \302\240 \302\240 \302\240 _clk_ccgr_enable(clk);\n" "> > +\n" - "> > + ? ? ? /* Handshake with MAX when LPM is entered. */\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CLPCR);\n" - "> > + ? ? ? reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CLPCR);\n" + "> > + \302\240 \302\240 \302\240 /* Handshake with MAX when LPM is entered. */\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CLPCR);\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CLPCR);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static void _clk_max_disable(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? _clk_ccgr_disable_inwait(clk);\n" + "> > + \302\240 \302\240 \302\240 _clk_ccgr_disable_inwait(clk);\n" "> > +\n" - "> > + ? ? ? /* No Handshake with MAX when LPM is entered as its disabled. */\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CLPCR);\n" - "> > + ? ? ? reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CLPCR);\n" + "> > + \302\240 \302\240 \302\240 /* No Handshake with MAX when LPM is entered as its disabled. */\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CLPCR);\n" + "> > + \302\240 \302\240 \302\240 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CLPCR);\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_ipg_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg, div;\n" - "> > + ? ? ? unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, div;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" - "> > + ? ? ? div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ?MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;\n" "> > +\n" - "> > + ? ? ? return parent_rate / div;\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / div;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_ipg_per_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg, prediv1, prediv2, podf;\n" - "> > + ? ? ? unsigned long parent_rate;\n" - "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" - "> > +\n" - "> > + ? ? ? if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {\n" - "> > + ? ? ? ? ? ? ? /* the main_bus_clk is the one before the DVFS engine */\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" - "> > + ? ? ? ? ? ? ? prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;\n" - "> > + ? ? ? ? ? ? ? prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ? ?MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;\n" - "> > + ? ? ? ? ? ? ? podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;\n" - "> > + ? ? ? ? ? ? ? return parent_rate / (prediv1 * prediv2 * podf);\n" - "> > + ? ? ? } else if (clk->parent == &ipg_clk) {\n" - "> > + ? ? ? ? ? ? ? return parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, prediv1, prediv2, podf;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* the main_bus_clk is the one before the DVFS engine */\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return parent_rate / (prediv1 * prediv2 * podf);\n" + "> > + \302\240 \302\240 \302\240 } else if (clk->parent == &ipg_clk) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return parent_rate;\n" "> \n" "> unnecessary braces\n" "> \n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? BUG();\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 BUG();\n" "> \n" "> ditto\n" "> \n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +}\n" "> > +\n" "> > +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCMR);\n" "> > +\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;\n" "> > +\n" - "> > + ? ? ? if (parent == &ipg_clk)\n" - "> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;\n" - "> > + ? ? ? else if (parent == &lp_apm_clk)\n" - "> > + ? ? ? ? ? ? ? reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;\n" - "> > + ? ? ? else if (parent != &main_bus_clk)\n" - "> > + ? ? ? ? ? ? ? return -EINVAL;\n" + "> > + \302\240 \302\240 \302\240 if (parent == &ipg_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 else if (parent == &lp_apm_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;\n" + "> > + \302\240 \302\240 \302\240 else if (parent != &main_bus_clk)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 return -EINVAL;\n" "> > +\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCMR);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CBCMR);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long clk_uart_get_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? u32 reg, prediv, podf;\n" - "> > + ? ? ? unsigned long parent_rate;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, prediv, podf;\n" + "> > + \302\240 \302\240 \302\240 unsigned long parent_rate;\n" "> > +\n" - "> > + ? ? ? parent_rate = clk_get_rate(clk->parent);\n" + "> > + \302\240 \302\240 \302\240 parent_rate = clk_get_rate(clk->parent);\n" "> > +\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CSCDR1);\n" - "> > + ? ? ? prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>\n" - "> > + ? ? ? ? ? ? ? ? MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;\n" - "> > + ? ? ? podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>\n" - "> > + ? ? ? ? ? ? ? MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CSCDR1);\n" + "> > + \302\240 \302\240 \302\240 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;\n" + "> > + \302\240 \302\240 \302\240 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;\n" "> > +\n" - "> > + ? ? ? return parent_rate / (prediv * podf);\n" + "> > + \302\240 \302\240 \302\240 return parent_rate / (prediv * podf);\n" "> > +}\n" "> > +\n" "> > +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)\n" "> > +{\n" - "> > + ? ? ? u32 reg, mux;\n" + "> > + \302\240 \302\240 \302\240 u32 reg, mux;\n" "> > +\n" - "> > + ? ? ? mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,\n" - "> > + ? ? ? ? ? ? ? ? ? ? ?&lp_apm_clk);\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;\n" - "> > + ? ? ? reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CSCMR1);\n" + "> > + \302\240 \302\240 \302\240 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240&lp_apm_clk);\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CSCMR1);\n" "> > +\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +static unsigned long get_high_reference_clock_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? return external_high_reference;\n" + "> > + \302\240 \302\240 \302\240 return external_high_reference;\n" "> > +}\n" "> > +\n" "> > +static unsigned long get_low_reference_clock_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? return external_low_reference;\n" + "> > + \302\240 \302\240 \302\240 return external_low_reference;\n" "> > +}\n" "> > +\n" "> > +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? return oscillator_reference;\n" + "> > + \302\240 \302\240 \302\240 return oscillator_reference;\n" "> > +}\n" "> > +\n" "> > +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)\n" "> > +{\n" - "> > + ? ? ? return ckih2_reference;\n" + "> > + \302\240 \302\240 \302\240 return ckih2_reference;\n" "> > +}\n" "> > +\n" "> > +/* External high frequency clock */\n" "> > +static struct clk ckih_clk = {\n" - "> > + ? ? ? .get_rate = get_high_reference_clock_rate,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = get_high_reference_clock_rate,\n" "> > +};\n" "> > +\n" "> > +static struct clk ckih2_clk = {\n" - "> > + ? ? ? .get_rate = get_ckih2_reference_clock_rate,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = get_ckih2_reference_clock_rate,\n" "> > +};\n" "> > +\n" "> > +static struct clk osc_clk = {\n" - "> > + ? ? ? .get_rate = get_oscillator_reference_clock_rate,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = get_oscillator_reference_clock_rate,\n" "> > +};\n" "> > +\n" "> > +/* External low frequency (32kHz) clock */\n" "> > +static struct clk ckil_clk = {\n" - "> > + ? ? ? .get_rate = get_low_reference_clock_rate,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = get_low_reference_clock_rate,\n" "> > +};\n" "> \n" "> That's why Jerremy is coming up with a clk_fixed, to address exactly such\n" @@ -721,234 +731,234 @@ "\n" "> > +\n" "> > +static struct clk pll1_main_clk = {\n" - "> > + ? ? ? .parent = &osc_clk,\n" - "> > + ? ? ? .get_rate = clk_pll_get_rate,\n" - "> > + ? ? ? .enable = _clk_pll_enable,\n" - "> > + ? ? ? .disable = _clk_pll_disable,\n" + "> > + \302\240 \302\240 \302\240 .parent = &osc_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_pll_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_pll_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_pll_disable,\n" "> > +};\n" "> > +\n" "> > +/* Clock tree block diagram (WIP):\n" - "> > + * ? ? CCM: Clock Controller Module\n" + "> > + * \302\240 \302\240 CCM: Clock Controller Module\n" "> > + *\n" "> > + * PLL output -> |\n" - "> > + * ? ? ? ? ? ? ? | CCM Switcher -> CCM_CLK_ROOT_GEN ->\n" + "> > + * \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 | CCM Switcher -> CCM_CLK_ROOT_GEN ->\n" "> > + * PLL bypass -> |\n" "> > + *\n" "> > + */\n" "> > +\n" "> > +/* PLL1 SW supplies to ARM core */\n" "> > +static struct clk pll1_sw_clk = {\n" - "> > + ? ? ? .parent = &pll1_main_clk,\n" - "> > + ? ? ? .set_parent = _clk_pll1_sw_set_parent,\n" - "> > + ? ? ? .get_rate = clk_pll1_sw_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .parent = &pll1_main_clk,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_pll1_sw_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_pll1_sw_get_rate,\n" "> > +};\n" "> > +\n" "> > +/* PLL2 SW supplies to AXI/AHB/IP buses */\n" "> > +static struct clk pll2_sw_clk = {\n" - "> > + ? ? ? .parent = &osc_clk,\n" - "> > + ? ? ? .get_rate = clk_pll_get_rate,\n" - "> > + ? ? ? .set_rate = _clk_pll_set_rate,\n" - "> > + ? ? ? .set_parent = _clk_pll2_sw_set_parent,\n" - "> > + ? ? ? .enable = _clk_pll_enable,\n" - "> > + ? ? ? .disable = _clk_pll_disable,\n" + "> > + \302\240 \302\240 \302\240 .parent = &osc_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_pll_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .set_rate = _clk_pll_set_rate,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_pll2_sw_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_pll_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_pll_disable,\n" "> > +};\n" "> > +\n" "> > +/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */\n" "> > +static struct clk pll3_sw_clk = {\n" - "> > + ? ? ? .parent = &osc_clk,\n" - "> > + ? ? ? .set_rate = _clk_pll_set_rate,\n" - "> > + ? ? ? .get_rate = clk_pll_get_rate,\n" - "> > + ? ? ? .enable = _clk_pll_enable,\n" - "> > + ? ? ? .disable = _clk_pll_disable,\n" + "> > + \302\240 \302\240 \302\240 .parent = &osc_clk,\n" + "> > + \302\240 \302\240 \302\240 .set_rate = _clk_pll_set_rate,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_pll_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_pll_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_pll_disable,\n" "> > +};\n" "> > +\n" "> > +/* Low-power Audio Playback Mode clock */\n" "> > +static struct clk lp_apm_clk = {\n" - "> > + ? ? ? .parent = &osc_clk,\n" - "> > + ? ? ? .set_parent = _clk_lp_apm_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .parent = &osc_clk,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_lp_apm_set_parent,\n" "> > +};\n" "> > +\n" "> > +static struct clk periph_apm_clk = {\n" - "> > + ? ? ? .parent = &pll1_sw_clk,\n" - "> > + ? ? ? .set_parent = _clk_periph_apm_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .parent = &pll1_sw_clk,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_periph_apm_set_parent,\n" "> > +};\n" "> > +\n" "> > +static struct clk cpu_clk = {\n" - "> > + ? ? ? .parent = &pll1_sw_clk,\n" - "> > + ? ? ? .get_rate = clk_arm_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .parent = &pll1_sw_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_arm_get_rate,\n" "> > +};\n" "> > +\n" "> > +static struct clk ahb_clk = {\n" - "> > + ? ? ? .parent = &main_bus_clk,\n" - "> > + ? ? ? .get_rate = clk_ahb_get_rate,\n" - "> > + ? ? ? .set_rate = _clk_ahb_set_rate,\n" - "> > + ? ? ? .round_rate = _clk_ahb_round_rate,\n" + "> > + \302\240 \302\240 \302\240 .parent = &main_bus_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_ahb_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .set_rate = _clk_ahb_set_rate,\n" + "> > + \302\240 \302\240 \302\240 .round_rate = _clk_ahb_round_rate,\n" "> > +};\n" "> > +\n" "> > +/* Main IP interface clock for access to registers */\n" "> > +static struct clk ipg_clk = {\n" - "> > + ? ? ? .parent = &ahb_clk,\n" - "> > + ? ? ? .get_rate = clk_ipg_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .parent = &ahb_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_ipg_get_rate,\n" "> > +};\n" "> > +\n" "> > +static struct clk ipg_perclk = {\n" - "> > + ? ? ? .parent = &lp_apm_clk,\n" - "> > + ? ? ? .get_rate = clk_ipg_per_get_rate,\n" - "> > + ? ? ? .set_parent = _clk_ipg_per_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .parent = &lp_apm_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_ipg_per_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_ipg_per_set_parent,\n" "> > +};\n" "> > +\n" "> > +static struct clk uart_root_clk = {\n" - "> > + ? ? ? .parent = &pll2_sw_clk,\n" - "> > + ? ? ? .get_rate = clk_uart_get_rate,\n" - "> > + ? ? ? .set_parent = _clk_uart_set_parent,\n" + "> > + \302\240 \302\240 \302\240 .parent = &pll2_sw_clk,\n" + "> > + \302\240 \302\240 \302\240 .get_rate = clk_uart_get_rate,\n" + "> > + \302\240 \302\240 \302\240 .set_parent = _clk_uart_set_parent,\n" "> > +};\n" "> > +\n" "> > +static struct clk ahb_max_clk = {\n" - "> > + ? ? ? .parent = &ahb_clk,\n" - "> > + ? ? ? .enable_reg = MXC_CCM_CCGR0,\n" - "> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,\n" - "> > + ? ? ? .enable = _clk_max_enable,\n" - "> > + ? ? ? .disable = _clk_max_disable,\n" + "> > + \302\240 \302\240 \302\240 .parent = &ahb_clk,\n" + "> > + \302\240 \302\240 \302\240 .enable_reg = MXC_CCM_CCGR0,\n" + "> > + \302\240 \302\240 \302\240 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_max_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_max_disable,\n" "> > +};\n" "> > +\n" "> > +static struct clk aips_tz1_clk = {\n" - "> > + ? ? ? .parent = &ahb_clk,\n" - "> > + ? ? ? .secondary = &ahb_max_clk,\n" - "> > + ? ? ? .enable_reg = MXC_CCM_CCGR0,\n" - "> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,\n" - "> > + ? ? ? .enable = _clk_ccgr_enable,\n" - "> > + ? ? ? .disable = _clk_ccgr_disable_inwait,\n" + "> > + \302\240 \302\240 \302\240 .parent = &ahb_clk,\n" + "> > + \302\240 \302\240 \302\240 .secondary = &ahb_max_clk,\n" + "> > + \302\240 \302\240 \302\240 .enable_reg = MXC_CCM_CCGR0,\n" + "> > + \302\240 \302\240 \302\240 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_ccgr_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_ccgr_disable_inwait,\n" "> > +};\n" "> > +\n" "> > +static struct clk aips_tz2_clk = {\n" - "> > + ? ? ? .parent = &ahb_clk,\n" - "> > + ? ? ? .secondary = &ahb_max_clk,\n" - "> > + ? ? ? .enable_reg = MXC_CCM_CCGR0,\n" - "> > + ? ? ? .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,\n" - "> > + ? ? ? .enable = _clk_ccgr_enable,\n" - "> > + ? ? ? .disable = _clk_ccgr_disable_inwait,\n" + "> > + \302\240 \302\240 \302\240 .parent = &ahb_clk,\n" + "> > + \302\240 \302\240 \302\240 .secondary = &ahb_max_clk,\n" + "> > + \302\240 \302\240 \302\240 .enable_reg = MXC_CCM_CCGR0,\n" + "> > + \302\240 \302\240 \302\240 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,\n" + "> > + \302\240 \302\240 \302\240 .enable = _clk_ccgr_enable,\n" + "> > + \302\240 \302\240 \302\240 .disable = _clk_ccgr_disable_inwait,\n" "> > +};\n" "> > +\n" "> > +static struct clk gpt_32k_clk = {\n" - "> > + ? ? ? .id = 0,\n" - "> > + ? ? ? .parent = &ckil_clk,\n" + "> > + \302\240 \302\240 \302\240 .id = 0,\n" + "> > + \302\240 \302\240 \302\240 .parent = &ckil_clk,\n" "> > +};\n" "> > +\n" - "> > +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) ? ?\\\n" - "> > + ? ? ? static struct clk name = { ? ? ? ? ? ? ? ? ? ? ?\\\n" - "> > + ? ? ? ? ? ? ? .id ? ? ? ? ? ? = i, ? ? ? ? ? ? ? ? ? ?\\\n" - "> > + ? ? ? ? ? ? ? .enable_reg ? ? = er, ? ? ? ? ? ? ? ? ? \\\n" - "> > + ? ? ? ? ? ? ? .enable_shift ? = es, ? ? ? ? ? ? ? ? ? \\\n" - "> > + ? ? ? ? ? ? ? .get_rate ? ? ? = gr, ? ? ? ? ? ? ? ? ? \\\n" - "> > + ? ? ? ? ? ? ? .set_rate ? ? ? = sr, ? ? ? ? ? ? ? ? ? \\\n" - "> > + ? ? ? ? ? ? ? .enable ? ? ? ? = _clk_ccgr_enable, ? ? \\\n" - "> > + ? ? ? ? ? ? ? .disable ? ? ? ?= _clk_ccgr_disable, ? ?\\\n" - "> > + ? ? ? ? ? ? ? .parent ? ? ? ? = p, ? ? ? ? ? ? ? ? ? ?\\\n" - "> > + ? ? ? ? ? ? ? .secondary ? ? ?= s, ? ? ? ? ? ? ? ? ? ?\\\n" - "> > + ? ? ? }\n" + "> > +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 static struct clk name = { \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .id \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 = i, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .enable_reg \302\240 \302\240 = er, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .enable_shift \302\240 = es, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .get_rate \302\240 \302\240 \302\240 = gr, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .set_rate \302\240 \302\240 \302\240 = sr, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .enable \302\240 \302\240 \302\240 \302\240 = _clk_ccgr_enable, \302\240 \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .disable \302\240 \302\240 \302\240 \302\240= _clk_ccgr_disable, \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .parent \302\240 \302\240 \302\240 \302\240 = p, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .secondary \302\240 \302\240 \302\240= s, \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\\\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +\n" "> > +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,\n" - "> > + ? get_rate, set_rate, parent, secondary); */\n" + "> > + \302\240 get_rate, set_rate, parent, secondary); */\n" "> > +\n" "> > +/* Shared peripheral bus arbiter */\n" "> > +DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, NULL);\n" "> > +\n" "> > +/* UART */\n" "> > +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &uart_root_clk, NULL);\n" "> > +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &uart_root_clk, NULL);\n" "> > +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &uart_root_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &uart_root_clk, NULL);\n" "> > +DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, &aips_tz1_clk);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, &aips_tz1_clk);\n" "> > +DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, &aips_tz1_clk);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, &aips_tz1_clk);\n" "> > +DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, &spba_clk);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, &spba_clk);\n" "> > +\n" "> > +/* GPT */\n" "> > +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_perclk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_perclk, NULL);\n" "> > +DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, NULL);\n" "> > +\n" "> > +/* FEC */\n" "> > +DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,\n" - "> > + ? ? ? NULL, ?NULL, &ipg_clk, NULL);\n" + "> > + \302\240 \302\240 \302\240 NULL, \302\240NULL, &ipg_clk, NULL);\n" "> > +\n" "> > +#define _REGISTER_CLOCK(d, n, c) \\\n" - "> > + ? ? ? { \\\n" - "> > + ? ? ? ? ? ? ? .dev_id = d, \\\n" - "> > + ? ? ? ? ? ? ? .con_id = n, \\\n" - "> > + ? ? ? ? ? ? ? .clk = &c, ? \\\n" - "> > + ? ? ? },\n" + "> > + \302\240 \302\240 \302\240 { \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .dev_id = d, \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .con_id = n, \\\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .clk = &c, \302\240 \\\n" + "> > + \302\240 \302\240 \302\240 },\n" "> > +\n" "> > +static struct clk_lookup lookups[] __initdata = {\n" - "> > + ? ? ? _REGISTER_CLOCK(\"imx-uart.0\", NULL, uart1_clk)\n" - "> > + ? ? ? _REGISTER_CLOCK(\"imx-uart.1\", NULL, uart2_clk)\n" - "> > + ? ? ? _REGISTER_CLOCK(\"imx-uart.2\", NULL, uart3_clk)\n" - "> > + ? ? ? _REGISTER_CLOCK(NULL, \"gpt\", gpt_clk)\n" - "> > + ? ? ? _REGISTER_CLOCK(\"fec.0\", NULL, fec_clk)\n" + "> > + \302\240 \302\240 \302\240 _REGISTER_CLOCK(\"imx-uart.0\", NULL, uart1_clk)\n" + "> > + \302\240 \302\240 \302\240 _REGISTER_CLOCK(\"imx-uart.1\", NULL, uart2_clk)\n" + "> > + \302\240 \302\240 \302\240 _REGISTER_CLOCK(\"imx-uart.2\", NULL, uart3_clk)\n" + "> > + \302\240 \302\240 \302\240 _REGISTER_CLOCK(NULL, \"gpt\", gpt_clk)\n" + "> > + \302\240 \302\240 \302\240 _REGISTER_CLOCK(\"fec.0\", NULL, fec_clk)\n" "> > +};\n" "> > +\n" "> > +static void clk_tree_init(void)\n" "> > +{\n" - "> > + ? ? ? u32 reg;\n" - "> > +\n" - "> > + ? ? ? ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);\n" - "> > +\n" - "> > + ? ? ? /*\n" - "> > + ? ? ? ?* Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at\n" - "> > + ? ? ? ?* 8MHz, its derived from lp_apm.\n" - "> > + ? ? ? ?* FIXME: Verify if true for all boards\n" - "> > + ? ? ? ?*/\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCDR);\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;\n" - "> > + ? ? ? reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;\n" - "> > + ? ? ? reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);\n" - "> > + ? ? ? __raw_writel(reg, MXC_CCM_CBCDR);\n" - "> > +\n" - "> > + ? ? ? /* set parent for pll1, pll2 and pll3 */\n" - "> > + ? ? ? pll1_main_clk.parent = &osc_clk;\n" - "> > + ? ? ? pll2_sw_clk.parent = &osc_clk;\n" - "> > + ? ? ? pll3_sw_clk.parent = &osc_clk;\n" - "> > +\n" - "> > + ? ? ? /* set ipg_perclk parent */\n" - "> > + ? ? ? ipg_perclk.parent = &lp_apm_clk;\n" - "> > + ? ? ? reg = __raw_readl(MXC_CCM_CBCMR);\n" - "> > + ? ? ? if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) {\n" - "> > + ? ? ? ? ? ? ? ipg_perclk.parent = &ipg_clk;\n" - "> > + ? ? ? } else {\n" - "> > + ? ? ? ? ? ? ? if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0)\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? ipg_perclk.parent = &main_bus_clk;\n" - "> > + ? ? ? }\n" + "> > + \302\240 \302\240 \302\240 u32 reg;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 /*\n" + "> > + \302\240 \302\240 \302\240 \302\240* Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at\n" + "> > + \302\240 \302\240 \302\240 \302\240* 8MHz, its derived from lp_apm.\n" + "> > + \302\240 \302\240 \302\240 \302\240* FIXME: Verify if true for all boards\n" + "> > + \302\240 \302\240 \302\240 \302\240*/\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCDR);\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;\n" + "> > + \302\240 \302\240 \302\240 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);\n" + "> > + \302\240 \302\240 \302\240 __raw_writel(reg, MXC_CCM_CBCDR);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 /* set parent for pll1, pll2 and pll3 */\n" + "> > + \302\240 \302\240 \302\240 pll1_main_clk.parent = &osc_clk;\n" + "> > + \302\240 \302\240 \302\240 pll2_sw_clk.parent = &osc_clk;\n" + "> > + \302\240 \302\240 \302\240 pll3_sw_clk.parent = &osc_clk;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 /* set ipg_perclk parent */\n" + "> > + \302\240 \302\240 \302\240 ipg_perclk.parent = &lp_apm_clk;\n" + "> > + \302\240 \302\240 \302\240 reg = __raw_readl(MXC_CCM_CBCMR);\n" + "> > + \302\240 \302\240 \302\240 if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ipg_perclk.parent = &ipg_clk;\n" + "> > + \302\240 \302\240 \302\240 } else {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ipg_perclk.parent = &main_bus_clk;\n" + "> > + \302\240 \302\240 \302\240 }\n" "> > +}\n" "> > +\n" "> > +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,\n" - "> > + ? ? ? ? ? ? ? ? ? ? ? unsigned long ckih1, unsigned long ckih2)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 unsigned long ckih1, unsigned long ckih2)\n" "> > +{\n" - "> > + ? ? ? int i;\n" + "> > + \302\240 \302\240 \302\240 int i;\n" "> > +\n" - "> > + ? ? ? external_low_reference = ckil;\n" - "> > + ? ? ? external_high_reference = ckih1;\n" - "> > + ? ? ? ckih2_reference = ckih2;\n" - "> > + ? ? ? oscillator_reference = osc;\n" + "> > + \302\240 \302\240 \302\240 external_low_reference = ckil;\n" + "> > + \302\240 \302\240 \302\240 external_high_reference = ckih1;\n" + "> > + \302\240 \302\240 \302\240 ckih2_reference = ckih2;\n" + "> > + \302\240 \302\240 \302\240 oscillator_reference = osc;\n" "> > +\n" - "> > + ? ? ? for (i = 0; i < ARRAY_SIZE(lookups); i++)\n" - "> > + ? ? ? ? ? ? ? clkdev_add(&lookups[i]);\n" + "> > + \302\240 \302\240 \302\240 for (i = 0; i < ARRAY_SIZE(lookups); i++)\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 clkdev_add(&lookups[i]);\n" "> > +\n" - "> > + ? ? ? clk_tree_init();\n" + "> > + \302\240 \302\240 \302\240 clk_tree_init();\n" "> > +\n" - "> > + ? ? ? clk_enable(&cpu_clk);\n" - "> > + ? ? ? clk_enable(&main_bus_clk);\n" + "> > + \302\240 \302\240 \302\240 clk_enable(&cpu_clk);\n" + "> > + \302\240 \302\240 \302\240 clk_enable(&main_bus_clk);\n" "> > +\n" - "> > + ? ? ? /* System timer */\n" - "> > + ? ? ? mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),\n" - "> > + ? ? ? ? ? ? ? MX51_MXC_INT_GPT);\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 /* System timer */\n" + "> > + \302\240 \302\240 \302\240 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 MX51_MXC_INT_GPT);\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c\n" "> > new file mode 100644\n" @@ -977,27 +987,27 @@ "> > +\n" "> > +static int __init post_cpu_init(void)\n" "> > +{\n" - "> > + ? ? ? unsigned int reg;\n" - "> > + ? ? ? void __iomem *base;\n" - "> > +\n" - "> > + ? ? ? if (cpu_is_mx51()) {\n" - "> > + ? ? ? ? ? ? ? base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x40);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x44);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x48);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x4C);\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(base + 0x50) & 0x00FFFFFF;\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, base + 0x50);\n" - "> > +\n" - "> > + ? ? ? ? ? ? ? base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x40);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x44);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x48);\n" - "> > + ? ? ? ? ? ? ? __raw_writel(0x0, base + 0x4C);\n" - "> > + ? ? ? ? ? ? ? reg = __raw_readl(base + 0x50) & 0x00FFFFFF;\n" - "> > + ? ? ? ? ? ? ? __raw_writel(reg, base + 0x50);\n" - "> > + ? ? ? }\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 unsigned int reg;\n" + "> > + \302\240 \302\240 \302\240 void __iomem *base;\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 if (cpu_is_mx51()) {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x40);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x44);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x48);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x4C);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, base + 0x50);\n" + "> > +\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x40);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x44);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x48);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(0x0, base + 0x4C);\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 __raw_writel(reg, base + 0x50);\n" + "> > + \302\240 \302\240 \302\240 }\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > +\n" "> > +postcore_initcall(post_cpu_init);\n" @@ -1020,16 +1030,16 @@ "> > +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__\n" "> > +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__\n" "> > +\n" - "> > +#define MX51_CCM_BASE ? ? ? ? ?MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)\n" - "> > +#define MX51_DPLL1_BASE ? ? ? ? ? ? ? ?MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)\n" - "> > +#define MX51_DPLL2_BASE ? ? ? ? ? ? ? ?MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)\n" + "> > +#define MX51_CCM_BASE \302\240 \302\240 \302\240 \302\240 \302\240MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)\n" + "> > +#define MX51_DPLL1_BASE \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)\n" + "> > +#define MX51_DPLL2_BASE \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)\n" "> \n" "> .... skipping register definitions ....\n" "> \n" - "> > +#define MXC_SRPGC_EMI_PUPSCR ? (MXC_SRPGC_EMI_BASE + 0x4)\n" - "> > +#define MXC_SRPGC_EMI_PDNSCR ? (MXC_SRPGC_EMI_BASE + 0x8)\n" + "> > +#define MXC_SRPGC_EMI_PUPSCR \302\240 (MXC_SRPGC_EMI_BASE + 0x4)\n" + "> > +#define MXC_SRPGC_EMI_PDNSCR \302\240 (MXC_SRPGC_EMI_BASE + 0x8)\n" "> > +\n" - "> > +#endif ? ? ? ? ? ? ? ? ? ? ? ? /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */\n" + "> > +#endif \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */\n" "> > diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c\n" "> > new file mode 100644\n" "> > index 0000000..55eb089\n" @@ -1052,85 +1062,85 @@ "> > +#include <mach/imx-uart.h>\n" "> > +\n" "> > +static struct resource uart0[] = {\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_UART1_BASE_ADDR,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_UART1_BASE_ADDR + 0x0B5,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM,\n" - "> > + ? ? ? }, {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART1,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART1,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ,\n" - "> > + ? ? ? },\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_UART1_BASE_ADDR,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_UART1_BASE_ADDR + 0x0B5,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_MEM,\n" + "> > + \302\240 \302\240 \302\240 }, {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_MXC_INT_UART1,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_MXC_INT_UART1,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_IRQ,\n" + "> > + \302\240 \302\240 \302\240 },\n" "> > +};\n" "> > +\n" "> > +struct platform_device mxc_uart_device0 = {\n" - "> > + ? ? ? .name = \"imx-uart\",\n" - "> > + ? ? ? .id = 0,\n" - "> > + ? ? ? .resource = uart0,\n" - "> > + ? ? ? .num_resources = ARRAY_SIZE(uart0),\n" + "> > + \302\240 \302\240 \302\240 .name = \"imx-uart\",\n" + "> > + \302\240 \302\240 \302\240 .id = 0,\n" + "> > + \302\240 \302\240 \302\240 .resource = uart0,\n" + "> > + \302\240 \302\240 \302\240 .num_resources = ARRAY_SIZE(uart0),\n" "> > +};\n" "> > +\n" "> > +static struct resource uart1[] = {\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_UART2_BASE_ADDR,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_UART2_BASE_ADDR + 0x0B5,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM,\n" - "> > + ? ? ? }, {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART2,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART2,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ,\n" - "> > + ? ? ? },\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_UART2_BASE_ADDR,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_UART2_BASE_ADDR + 0x0B5,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_MEM,\n" + "> > + \302\240 \302\240 \302\240 }, {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_MXC_INT_UART2,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_MXC_INT_UART2,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_IRQ,\n" + "> > + \302\240 \302\240 \302\240 },\n" "> > +};\n" "> > +\n" "> > +struct platform_device mxc_uart_device1 = {\n" - "> > + ? ? ? .name = \"imx-uart\",\n" - "> > + ? ? ? .id = 1,\n" - "> > + ? ? ? .resource = uart1,\n" - "> > + ? ? ? .num_resources = ARRAY_SIZE(uart1),\n" + "> > + \302\240 \302\240 \302\240 .name = \"imx-uart\",\n" + "> > + \302\240 \302\240 \302\240 .id = 1,\n" + "> > + \302\240 \302\240 \302\240 .resource = uart1,\n" + "> > + \302\240 \302\240 \302\240 .num_resources = ARRAY_SIZE(uart1),\n" "> > +};\n" "> > +\n" "> > +static struct resource uart2[] = {\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_UART3_BASE_ADDR,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_UART3_BASE_ADDR + 0x0B5,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM,\n" - "> > + ? ? ? }, {\n" - "> > + ? ? ? ? ? ? ? .start = MX51_MXC_INT_UART3,\n" - "> > + ? ? ? ? ? ? ? .end = MX51_MXC_INT_UART3,\n" - "> > + ? ? ? ? ? ? ? .flags = IORESOURCE_IRQ,\n" - "> > + ? ? ? },\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_UART3_BASE_ADDR,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_UART3_BASE_ADDR + 0x0B5,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_MEM,\n" + "> > + \302\240 \302\240 \302\240 }, {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start = MX51_MXC_INT_UART3,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end = MX51_MXC_INT_UART3,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags = IORESOURCE_IRQ,\n" + "> > + \302\240 \302\240 \302\240 },\n" "> > +};\n" "> > +\n" "> > +struct platform_device mxc_uart_device2 = {\n" - "> > + ? ? ? .name = \"imx-uart\",\n" - "> > + ? ? ? .id = 2,\n" - "> > + ? ? ? .resource = uart2,\n" - "> > + ? ? ? .num_resources = ARRAY_SIZE(uart2),\n" + "> > + \302\240 \302\240 \302\240 .name = \"imx-uart\",\n" + "> > + \302\240 \302\240 \302\240 .id = 2,\n" + "> > + \302\240 \302\240 \302\240 .resource = uart2,\n" + "> > + \302\240 \302\240 \302\240 .num_resources = ARRAY_SIZE(uart2),\n" "> > +};\n" "> > +\n" "> > +static struct resource mxc_fec_resources[] = {\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ? ? ? ? .start ?= MX51_MXC_FEC_BASE_ADDR,\n" - "> > + ? ? ? ? ? ? ? .end ? ?= MX51_MXC_FEC_BASE_ADDR + 0xfff,\n" - "> > + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,\n" - "> > + ? ? ? }, {\n" - "> > + ? ? ? ? ? ? ? .start ?= MX51_MXC_INT_FEC,\n" - "> > + ? ? ? ? ? ? ? .end ? ?= MX51_MXC_INT_FEC,\n" - "> > + ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,\n" - "> > + ? ? ? },\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start \302\240= MX51_MXC_FEC_BASE_ADDR,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end \302\240 \302\240= MX51_MXC_FEC_BASE_ADDR + 0xfff,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags \302\240= IORESOURCE_MEM,\n" + "> > + \302\240 \302\240 \302\240 }, {\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .start \302\240= MX51_MXC_INT_FEC,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .end \302\240 \302\240= MX51_MXC_INT_FEC,\n" + "> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 .flags \302\240= IORESOURCE_IRQ,\n" + "> > + \302\240 \302\240 \302\240 },\n" "> > +};\n" "> > +\n" "> > +struct platform_device mxc_fec_device = {\n" - "> > + ? ? ? .name = \"fec\",\n" - "> > + ? ? ? .id = 0,\n" - "> > + ? ? ? .num_resources = ARRAY_SIZE(mxc_fec_resources),\n" - "> > + ? ? ? .resource = mxc_fec_resources,\n" + "> > + \302\240 \302\240 \302\240 .name = \"fec\",\n" + "> > + \302\240 \302\240 \302\240 .id = 0,\n" + "> > + \302\240 \302\240 \302\240 .num_resources = ARRAY_SIZE(mxc_fec_resources),\n" + "> > + \302\240 \302\240 \302\240 .resource = mxc_fec_resources,\n" "> > +};\n" "> > +\n" "> > +/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */\n" "> > +int __init mxc_register_gpios(void)\n" "> > +{\n" - "> > + ? ? ? return 0;\n" + "> > + \302\240 \302\240 \302\240 return 0;\n" "> > +}\n" "> > diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h\n" "> > new file mode 100644\n" @@ -1152,7 +1162,7 @@ "> > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.\n" "> > + *\n" "> > + * The code contained herein is licensed under the GNU General Public\n" - "> > + * License. ?You may obtain a copy of the GNU General Public License\n" + "> > + * License. \302\240You may obtain a copy of the GNU General Public License\n" "> > + * Version 2 or later at the following locations:\n" "> > + *\n" "> > + * http://www.opensource.org/licenses/gpl-license.html\n" @@ -1174,41 +1184,41 @@ "> > + * Define the MX51 memory map.\n" "> > + */\n" "> > +static struct map_desc mxc_io_desc[] __initdata = {\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_IRAM_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_IRAM_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_DEBUG_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_DEBUG_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_TZIC_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_TZIC_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_AIPS1_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_AIPS1_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_SPBA0_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_SPBA0_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_AIPS2_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_AIPS2_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" - "> > + ? ? ? {\n" - "> > + ? ? ? ?.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,\n" - "> > + ? ? ? ?.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),\n" - "> > + ? ? ? ?.length = MX51_NFC_AXI_SIZE,\n" - "> > + ? ? ? ?.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_IRAM_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_IRAM_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_DEBUG_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_DEBUG_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_TZIC_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_TZIC_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_AIPS1_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_AIPS1_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_SPBA0_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_SPBA0_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_AIPS2_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_AIPS2_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" + "> > + \302\240 \302\240 \302\240 {\n" + "> > + \302\240 \302\240 \302\240 \302\240.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,\n" + "> > + \302\240 \302\240 \302\240 \302\240.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),\n" + "> > + \302\240 \302\240 \302\240 \302\240.length = MX51_NFC_AXI_SIZE,\n" + "> > + \302\240 \302\240 \302\240 \302\240.type = MT_DEVICE},\n" "> \n" "> Weird alignment, guess due to leading white spaces?\n" "\n" @@ -1222,7 +1232,7 @@ "/Amit\n" "-- \n" "----------------------------------------------------------------------\n" - "Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com\n" + "Amit Kucheria, Kernel Engineer || amit.kucheria@canonical.com\n" ---------------------------------------------------------------------- -c59855fa1758e1c7e23d879a4b3fbf8a805076e7b9b786995748c8169c2c37bd +9fa1187114a864c8f26c2facea05e026f16da845e6b64507f682751139ccd7b8
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.