diff for duplicates of <20100211034520.GC21755@atomide.com> diff --git a/a/1.txt b/N1/1.txt index a9db895..8b13789 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,282 +1 @@ ->From 2cf160e424cdb4efa29e1078841a649a44f50c79 Mon Sep 17 00:00:00 2001 -From: Vimal Singh <vimalsingh@ti.com> -Date: Wed, 10 Feb 2010 18:22:54 -0800 -Subject: [PATCH] omap2/3/4: Introducing 'gpmc-nand.c' for GPMC specific NAND init -Introducing 'gpmc-nand.c' for GPMC specific NAND init. -For example: GPMC timing parameters and all. -This patch also migrates gpmc related calls from 'nand/omap2.c' -to 'gpmc-nand.c'. - -Signed-off-by: Vimal Singh <vimalsingh@ti.com> -Signed-off-by: Tony Lindgren <tony@atomide.com> - -diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile -index 492cf16..0b17dca 100644 ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -135,5 +135,8 @@ obj-y += usb-ehci.o - onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o - obj-y += $(onenand-m) $(onenand-y) - -+nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o -+obj-y += $(nand-m) $(nand-y) -+ - smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o - obj-y += $(smc91x-m) $(smc91x-y) -diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c -new file mode 100644 -index 0000000..64d74f0 ---- /dev/null -+++ b/arch/arm/mach-omap2/gpmc-nand.c -@@ -0,0 +1,139 @@ -+/* -+ * gpmc-nand.c -+ * -+ * Copyright (C) 2009 Texas Instruments -+ * Vimal Singh <vimalsingh@ti.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/platform_device.h> -+#include <linux/io.h> -+ -+#include <asm/mach/flash.h> -+ -+#include <plat/nand.h> -+#include <plat/board.h> -+#include <plat/gpmc.h> -+ -+#define WR_RD_PIN_MONITORING 0x00600000 -+ -+static struct omap_nand_platform_data *gpmc_nand_data; -+ -+static struct resource gpmc_nand_resource = { -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct platform_device gpmc_nand_device = { -+ .name = "omap2-nand", -+ .id = 0, -+ .num_resources = 1, -+ .resource = &gpmc_nand_resource, -+}; -+ -+static int omap2_nand_gpmc_retime(void) -+{ -+ struct gpmc_timings t; -+ int err; -+ -+ memset(&t, 0, sizeof(t)); -+ t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); -+ t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); -+ t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); -+ -+ /* Read */ -+ t.adv_rd_off = gpmc_round_ns_to_ticks( -+ gpmc_nand_data->gpmc_t->adv_rd_off); -+ t.oe_on = t.adv_on; -+ t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access); -+ t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off); -+ t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off); -+ t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle); -+ -+ /* Write */ -+ t.adv_wr_off = gpmc_round_ns_to_ticks( -+ gpmc_nand_data->gpmc_t->adv_wr_off); -+ t.we_on = t.oe_on; -+ if (cpu_is_omap34xx()) { -+ t.wr_data_mux_bus = gpmc_round_ns_to_ticks( -+ gpmc_nand_data->gpmc_t->wr_data_mux_bus); -+ t.wr_access = gpmc_round_ns_to_ticks( -+ gpmc_nand_data->gpmc_t->wr_access); -+ } -+ t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off); -+ t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off); -+ t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); -+ -+ /* Configure GPMC */ -+ gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, -+ GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | -+ GPMC_CONFIG1_DEVICETYPE_NAND); -+ -+ err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+static int gpmc_nand_setup(void) -+{ -+ struct device *dev = &gpmc_nand_device.dev; -+ -+ /* Set timings in GPMC */ -+ if (omap2_nand_gpmc_retime() < 0) { -+ dev_err(dev, "Unable to set gpmc timings\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) -+{ -+ unsigned int val; -+ int err = 0; -+ struct device *dev = &gpmc_nand_device.dev; -+ -+ gpmc_nand_data = _nand_data; -+ gpmc_nand_data->nand_setup = gpmc_nand_setup; -+ gpmc_nand_device.dev.platform_data = gpmc_nand_data; -+ -+ err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, -+ &gpmc_nand_data->phys_base); -+ if (err < 0) { -+ dev_err(dev, "Cannot request GPMC CS\n"); -+ return err; -+ } -+ -+ err = gpmc_nand_setup(); -+ if (err < 0) { -+ dev_err(dev, "NAND platform setup failed: %d\n", err); -+ return err; -+ } -+ -+ /* Enable RD PIN Monitoring Reg */ -+ if (gpmc_nand_data->dev_ready) { -+ val = gpmc_cs_read_reg(gpmc_nand_data->cs, -+ GPMC_CS_CONFIG1); -+ val |= WR_RD_PIN_MONITORING; -+ gpmc_cs_write_reg(gpmc_nand_data->cs, -+ GPMC_CS_CONFIG1, val); -+ } -+ -+ err = platform_device_register(&gpmc_nand_device); -+ if (err < 0) { -+ dev_err(dev, "Unable to register NAND device\n"); -+ goto out_free_cs; -+ } -+ -+ return 0; -+ -+out_free_cs: -+ gpmc_cs_free(gpmc_nand_data->cs); -+ -+ return err; -+} -diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h -index 631a7be..6ba88d2 100644 ---- a/arch/arm/plat-omap/include/plat/nand.h -+++ b/arch/arm/plat-omap/include/plat/nand.h -@@ -15,10 +15,18 @@ struct omap_nand_platform_data { - int cs; - int gpio_irq; - struct mtd_partition *parts; -+ struct gpmc_timings *gpmc_t; - int nr_parts; -- int (*nand_setup)(void __iomem *); -+ int (*nand_setup)(void); - int (*dev_ready)(struct omap_nand_platform_data *); - int dma_channel; -+ unsigned long phys_base; - void __iomem *gpmc_cs_baseaddr; - void __iomem *gpmc_baseaddr; -+ int devsize; - }; -+ -+/* size (4 KiB) for IO mapping */ -+#define NAND_IO_SIZE SZ_4K -+ -+extern int gpmc_nand_init(struct omap_nand_platform_data *d); -diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c -index 1bb799f..26aec00 100644 ---- a/drivers/mtd/nand/omap2.c -+++ b/drivers/mtd/nand/omap2.c -@@ -30,12 +30,8 @@ - - #define DRIVER_NAME "omap2-nand" - --/* size (4 KiB) for IO mapping */ --#define NAND_IO_SIZE SZ_4K -- - #define NAND_WP_OFF 0 - #define NAND_WP_BIT 0x00000010 --#define WR_RD_PIN_MONITORING 0x00600000 - - #define GPMC_BUF_FULL 0x00000001 - #define GPMC_BUF_EMPTY 0x00000000 -@@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) - struct omap_nand_info *info; - struct omap_nand_platform_data *pdata; - int err; -- unsigned long val; -- - - pdata = pdev->dev.platform_data; - if (pdata == NULL) { -@@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) - info->gpmc_cs = pdata->cs; - info->gpmc_baseaddr = pdata->gpmc_baseaddr; - info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; -+ info->phys_base = pdata->phys_base; - - info->mtd.priv = &info->nand; - info->mtd.name = dev_name(&pdev->dev); - info->mtd.owner = THIS_MODULE; - -- err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); -- if (err < 0) { -- dev_err(&pdev->dev, "Cannot request GPMC CS\n"); -- goto out_free_info; -- } -- -- /* Enable RD PIN Monitoring Reg */ -- if (pdata->dev_ready) { -- val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); -- val |= WR_RD_PIN_MONITORING; -- gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); -- } -- -- val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); -- val &= ~(0xf << 8); -- val |= (0xc & 0xf) << 8; -- gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); -+ info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; -+ info->nand.options |= NAND_SKIP_BBTSCAN; - - /* NAND write protect off */ - omap_nand_wp(&info->mtd, NAND_WP_OFF); -@@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) - if (!request_mem_region(info->phys_base, NAND_IO_SIZE, - pdev->dev.driver->name)) { - err = -EBUSY; -- goto out_free_cs; -+ goto out_free_info; - } - - info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); -@@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) - info->nand.chip_delay = 50; - } - -- info->nand.options |= NAND_SKIP_BBTSCAN; -- if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) -- == 0x1000) -- info->nand.options |= NAND_BUSWIDTH_16; -- - if (use_prefetch) { - /* copy the virtual address of nand base for fifo access */ - info->nand_pref_fifo_add = info->nand.IO_ADDR_R; -@@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev) - - out_release_mem_region: - release_mem_region(info->phys_base, NAND_IO_SIZE); --out_free_cs: -- gpmc_cs_free(info->gpmc_cs); - out_free_info: - kfree(info); diff --git a/a/content_digest b/N1/content_digest index 1abd80a..b132c6d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,292 +1,9 @@ "ref\020100211033310.1624.80025.stgit@baageli.muru.com\0" - "From\0Tony Lindgren <tony@atomide.com>\0" + "From\0tony@atomide.com (Tony Lindgren)\0" "Subject\0[PATCH 15/17] omap2/3/4: Introducing 'gpmc-nand.c' for GPMC specific NAND init\0" "Date\0Wed, 10 Feb 2010 19:45:21 -0800\0" "To\0linux-arm-kernel@lists.infradead.org\0" - "Cc\0linux-omap@vger.kernel.org\0" "\00:1\0" "b\0" - ">From 2cf160e424cdb4efa29e1078841a649a44f50c79 Mon Sep 17 00:00:00 2001\n" - "From: Vimal Singh <vimalsingh@ti.com>\n" - "Date: Wed, 10 Feb 2010 18:22:54 -0800\n" - "Subject: [PATCH] omap2/3/4: Introducing 'gpmc-nand.c' for GPMC specific NAND init\n" - "\n" - "Introducing 'gpmc-nand.c' for GPMC specific NAND init.\n" - "For example: GPMC timing parameters and all.\n" - "This patch also migrates gpmc related calls from 'nand/omap2.c'\n" - "to 'gpmc-nand.c'.\n" - "\n" - "Signed-off-by: Vimal Singh <vimalsingh@ti.com>\n" - "Signed-off-by: Tony Lindgren <tony@atomide.com>\n" - "\n" - "diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile\n" - "index 492cf16..0b17dca 100644\n" - "--- a/arch/arm/mach-omap2/Makefile\n" - "+++ b/arch/arm/mach-omap2/Makefile\n" - "@@ -135,5 +135,8 @@ obj-y\t\t\t\t\t+= usb-ehci.o\n" - " onenand-$(CONFIG_MTD_ONENAND_OMAP2)\t:= gpmc-onenand.o\n" - " obj-y\t\t\t\t\t+= $(onenand-m) $(onenand-y)\n" - " \n" - "+nand-$(CONFIG_MTD_NAND_OMAP2)\t\t:= gpmc-nand.o\n" - "+obj-y\t\t\t\t\t+= $(nand-m) $(nand-y)\n" - "+\n" - " smc91x-$(CONFIG_SMC91X)\t\t\t:= gpmc-smc91x.o\n" - " obj-y\t\t\t\t\t+= $(smc91x-m) $(smc91x-y)\n" - "diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c\n" - "new file mode 100644\n" - "index 0000000..64d74f0\n" - "--- /dev/null\n" - "+++ b/arch/arm/mach-omap2/gpmc-nand.c\n" - "@@ -0,0 +1,139 @@\n" - "+/*\n" - "+ * gpmc-nand.c\n" - "+ *\n" - "+ * Copyright (C) 2009 Texas Instruments\n" - "+ * Vimal Singh <vimalsingh@ti.com>\n" - "+ *\n" - "+ * This program is free software; you can redistribute it and/or modify\n" - "+ * it under the terms of the GNU General Public License version 2 as\n" - "+ * published by the Free Software Foundation.\n" - "+ */\n" - "+\n" - "+#include <linux/kernel.h>\n" - "+#include <linux/platform_device.h>\n" - "+#include <linux/io.h>\n" - "+\n" - "+#include <asm/mach/flash.h>\n" - "+\n" - "+#include <plat/nand.h>\n" - "+#include <plat/board.h>\n" - "+#include <plat/gpmc.h>\n" - "+\n" - "+#define WR_RD_PIN_MONITORING\t0x00600000\n" - "+\n" - "+static struct omap_nand_platform_data *gpmc_nand_data;\n" - "+\n" - "+static struct resource gpmc_nand_resource = {\n" - "+\t.flags\t\t= IORESOURCE_MEM,\n" - "+};\n" - "+\n" - "+static struct platform_device gpmc_nand_device = {\n" - "+\t.name\t\t= \"omap2-nand\",\n" - "+\t.id\t\t= 0,\n" - "+\t.num_resources\t= 1,\n" - "+\t.resource\t= &gpmc_nand_resource,\n" - "+};\n" - "+\n" - "+static int omap2_nand_gpmc_retime(void)\n" - "+{\n" - "+\tstruct gpmc_timings t;\n" - "+\tint err;\n" - "+\n" - "+\tmemset(&t, 0, sizeof(t));\n" - "+\tt.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);\n" - "+\tt.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);\n" - "+\tt.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);\n" - "+\n" - "+\t/* Read */\n" - "+\tt.adv_rd_off = gpmc_round_ns_to_ticks(\n" - "+\t\t\t\tgpmc_nand_data->gpmc_t->adv_rd_off);\n" - "+\tt.oe_on = t.adv_on;\n" - "+\tt.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access);\n" - "+\tt.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off);\n" - "+\tt.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off);\n" - "+\tt.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle);\n" - "+\n" - "+\t/* Write */\n" - "+\tt.adv_wr_off = gpmc_round_ns_to_ticks(\n" - "+\t\t\t\tgpmc_nand_data->gpmc_t->adv_wr_off);\n" - "+\tt.we_on = t.oe_on;\n" - "+\tif (cpu_is_omap34xx()) {\n" - "+\t t.wr_data_mux_bus =\tgpmc_round_ns_to_ticks(\n" - "+\t\t\t\tgpmc_nand_data->gpmc_t->wr_data_mux_bus);\n" - "+\t t.wr_access = gpmc_round_ns_to_ticks(\n" - "+\t\t\t\tgpmc_nand_data->gpmc_t->wr_access);\n" - "+\t}\n" - "+\tt.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off);\n" - "+\tt.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);\n" - "+\tt.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);\n" - "+\n" - "+\t/* Configure GPMC */\n" - "+\tgpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1,\n" - "+\t\t\tGPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) |\n" - "+\t\t\tGPMC_CONFIG1_DEVICETYPE_NAND);\n" - "+\n" - "+\terr = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);\n" - "+\tif (err)\n" - "+\t\treturn err;\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+static int gpmc_nand_setup(void)\n" - "+{\n" - "+\tstruct device *dev = &gpmc_nand_device.dev;\n" - "+\n" - "+\t/* Set timings in GPMC */\n" - "+\tif (omap2_nand_gpmc_retime() < 0) {\n" - "+\t\tdev_err(dev, \"Unable to set gpmc timings\\n\");\n" - "+\t\treturn -EINVAL;\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+}\n" - "+\n" - "+int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)\n" - "+{\n" - "+\tunsigned int val;\n" - "+\tint err\t= 0;\n" - "+\tstruct device *dev = &gpmc_nand_device.dev;\n" - "+\n" - "+\tgpmc_nand_data = _nand_data;\n" - "+\tgpmc_nand_data->nand_setup = gpmc_nand_setup;\n" - "+\tgpmc_nand_device.dev.platform_data = gpmc_nand_data;\n" - "+\n" - "+\terr = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,\n" - "+\t\t\t\t&gpmc_nand_data->phys_base);\n" - "+\tif (err < 0) {\n" - "+\t\tdev_err(dev, \"Cannot request GPMC CS\\n\");\n" - "+\t\treturn err;\n" - "+\t}\n" - "+\n" - "+\terr = gpmc_nand_setup();\n" - "+\tif (err < 0) {\n" - "+\t\tdev_err(dev, \"NAND platform setup failed: %d\\n\", err);\n" - "+\t\treturn err;\n" - "+\t}\n" - "+\n" - "+\t/* Enable RD PIN Monitoring Reg */\n" - "+\tif (gpmc_nand_data->dev_ready) {\n" - "+\t\tval = gpmc_cs_read_reg(gpmc_nand_data->cs,\n" - "+\t\t\t\t\t\t GPMC_CS_CONFIG1);\n" - "+\t\tval |= WR_RD_PIN_MONITORING;\n" - "+\t\tgpmc_cs_write_reg(gpmc_nand_data->cs,\n" - "+\t\t\t\t\t\tGPMC_CS_CONFIG1, val);\n" - "+\t}\n" - "+\n" - "+\terr = platform_device_register(&gpmc_nand_device);\n" - "+\tif (err < 0) {\n" - "+\t\tdev_err(dev, \"Unable to register NAND device\\n\");\n" - "+\t\tgoto out_free_cs;\n" - "+\t}\n" - "+\n" - "+\treturn 0;\n" - "+\n" - "+out_free_cs:\n" - "+\tgpmc_cs_free(gpmc_nand_data->cs);\n" - "+\n" - "+\treturn err;\n" - "+}\n" - "diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h\n" - "index 631a7be..6ba88d2 100644\n" - "--- a/arch/arm/plat-omap/include/plat/nand.h\n" - "+++ b/arch/arm/plat-omap/include/plat/nand.h\n" - "@@ -15,10 +15,18 @@ struct omap_nand_platform_data {\n" - " \tint\t\t\tcs;\n" - " \tint\t\t\tgpio_irq;\n" - " \tstruct mtd_partition\t*parts;\n" - "+\tstruct gpmc_timings\t*gpmc_t;\n" - " \tint\t\t\tnr_parts;\n" - "-\tint\t\t\t(*nand_setup)(void __iomem *);\n" - "+\tint\t\t\t(*nand_setup)(void);\n" - " \tint\t\t\t(*dev_ready)(struct omap_nand_platform_data *);\n" - " \tint\t\t\tdma_channel;\n" - "+\tunsigned long\t\tphys_base;\n" - " \tvoid __iomem\t\t*gpmc_cs_baseaddr;\n" - " \tvoid __iomem\t\t*gpmc_baseaddr;\n" - "+\tint\t\t\tdevsize;\n" - " };\n" - "+\n" - "+/* size (4 KiB) for IO mapping */\n" - "+#define\tNAND_IO_SIZE\tSZ_4K\n" - "+\n" - "+extern int gpmc_nand_init(struct omap_nand_platform_data *d);\n" - "diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c\n" - "index 1bb799f..26aec00 100644\n" - "--- a/drivers/mtd/nand/omap2.c\n" - "+++ b/drivers/mtd/nand/omap2.c\n" - "@@ -30,12 +30,8 @@\n" - " \n" - " #define\tDRIVER_NAME\t\"omap2-nand\"\n" - " \n" - "-/* size (4 KiB) for IO mapping */\n" - "-#define\tNAND_IO_SIZE\tSZ_4K\n" - "-\n" - " #define\tNAND_WP_OFF\t0\n" - " #define NAND_WP_BIT\t0x00000010\n" - "-#define WR_RD_PIN_MONITORING\t0x00600000\n" - " \n" - " #define\tGPMC_BUF_FULL\t0x00000001\n" - " #define\tGPMC_BUF_EMPTY\t0x00000000\n" - "@@ -882,8 +878,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)\n" - " \tstruct omap_nand_info\t\t*info;\n" - " \tstruct omap_nand_platform_data\t*pdata;\n" - " \tint\t\t\t\terr;\n" - "-\tunsigned long \t\t\tval;\n" - "-\n" - " \n" - " \tpdata = pdev->dev.platform_data;\n" - " \tif (pdata == NULL) {\n" - "@@ -905,28 +899,14 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)\n" - " \tinfo->gpmc_cs\t\t= pdata->cs;\n" - " \tinfo->gpmc_baseaddr\t= pdata->gpmc_baseaddr;\n" - " \tinfo->gpmc_cs_baseaddr\t= pdata->gpmc_cs_baseaddr;\n" - "+\tinfo->phys_base\t\t= pdata->phys_base;\n" - " \n" - " \tinfo->mtd.priv\t\t= &info->nand;\n" - " \tinfo->mtd.name\t\t= dev_name(&pdev->dev);\n" - " \tinfo->mtd.owner\t\t= THIS_MODULE;\n" - " \n" - "-\terr = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);\n" - "-\tif (err < 0) {\n" - "-\t\tdev_err(&pdev->dev, \"Cannot request GPMC CS\\n\");\n" - "-\t\tgoto out_free_info;\n" - "-\t}\n" - "-\n" - "-\t/* Enable RD PIN Monitoring Reg */\n" - "-\tif (pdata->dev_ready) {\n" - "-\t\tval = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);\n" - "-\t\tval |= WR_RD_PIN_MONITORING;\n" - "-\t\tgpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);\n" - "-\t}\n" - "-\n" - "-\tval = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);\n" - "-\tval &= ~(0xf << 8);\n" - "-\tval |= (0xc & 0xf) << 8;\n" - "-\tgpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);\n" - "+\tinfo->nand.options\t|= pdata->devsize ? NAND_BUSWIDTH_16 : 0;\n" - "+\tinfo->nand.options\t|= NAND_SKIP_BBTSCAN;\n" - " \n" - " \t/* NAND write protect off */\n" - " \tomap_nand_wp(&info->mtd, NAND_WP_OFF);\n" - "@@ -934,7 +914,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)\n" - " \tif (!request_mem_region(info->phys_base, NAND_IO_SIZE,\n" - " \t\t\t\tpdev->dev.driver->name)) {\n" - " \t\terr = -EBUSY;\n" - "-\t\tgoto out_free_cs;\n" - "+\t\tgoto out_free_info;\n" - " \t}\n" - " \n" - " \tinfo->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);\n" - "@@ -963,11 +943,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)\n" - " \t\tinfo->nand.chip_delay = 50;\n" - " \t}\n" - " \n" - "-\tinfo->nand.options |= NAND_SKIP_BBTSCAN;\n" - "-\tif ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)\n" - "-\t\t\t\t\t\t\t\t== 0x1000)\n" - "-\t\tinfo->nand.options |= NAND_BUSWIDTH_16;\n" - "-\n" - " \tif (use_prefetch) {\n" - " \t\t/* copy the virtual address of nand base for fifo access */\n" - " \t\tinfo->nand_pref_fifo_add = info->nand.IO_ADDR_R;\n" - "@@ -1043,8 +1018,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)\n" - " \n" - " out_release_mem_region:\n" - " \trelease_mem_region(info->phys_base, NAND_IO_SIZE);\n" - "-out_free_cs:\n" - "-\tgpmc_cs_free(info->gpmc_cs);\n" - " out_free_info:\n" - " \tkfree(info);" -616e6ab6354cd1f59a011bc8f1bd32985eb5239f0b837bed148fb3a5d7082258 +68f605202037edbb789241600d1564e6164fea9e3d00ca2956d7709e62da616d
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