diff for duplicates of <20100319013521.GP2900@atomide.com> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 261ea6c..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/x-diff; charset=us-ascii -Content-Disposition: inline; filename="arm-check-tls.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 266ac15..0000000 --- a/a/2.txt +++ /dev/null @@ -1,196 +0,0 @@ ->From 81d4bf2481c4ef5fd80261605977b5f55e4515e4 Mon Sep 17 00:00:00 2001 -From: Tony Lindgren <tony@atomide.com> -Date: Thu, 18 Mar 2010 12:02:43 -0700 -Subject: [PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6 - -The TLS register is only available on V6 r1p0 and later. -Test for it and use it if available. - -Signed-off-by: Tony Lindgren <tony@atomide.com> - -diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h -index f7bd52b..c1062c3 100644 ---- a/arch/arm/include/asm/hwcap.h -+++ b/arch/arm/include/asm/hwcap.h -@@ -19,6 +19,7 @@ - #define HWCAP_NEON 4096 - #define HWCAP_VFPv3 8192 - #define HWCAP_VFPv3D16 16384 -+#define HWCAP_TLS 32768 - - #if defined(__KERNEL__) && !defined(__ASSEMBLY__) - /* -diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S -index 6c5cf36..5a5aac8 100644 ---- a/arch/arm/kernel/entry-armv.S -+++ b/arch/arm/kernel/entry-armv.S -@@ -739,11 +739,13 @@ ENTRY(__switch_to) - #ifdef CONFIG_MMU - ldr r6, [r2, #TI_CPU_DOMAIN] - #endif --#if defined(CONFIG_HAS_TLS_REG) -- mcr p15, 0, r3, c13, c0, 3 @ set TLS register --#elif !defined(CONFIG_TLS_REG_EMUL) -- mov r4, #0xffff0fff -- str r3, [r4, #-15] @ TLS val at 0xffff0ff0 -+#if !defined(CONFIG_TLS_REG_EMUL) -+ ldr r4, =elf_hwcap -+ ldr r4, [r4, #0] -+ tst r4, #HWCAP_TLS @ hardware with TLS? -+ mcrne p15, 0, r3, c13, c0, 3 @ set TLS register -+ moveq r4, #0xffff0fff -+ streq r3, [r4, #-15] @ TLS val at 0xffff0ff0 - #endif - #ifdef CONFIG_MMU - mcr p15, 0, r6, c3, c0, 0 @ Set domain register -@@ -1009,15 +1011,12 @@ kuser_cmpxchg_fixup: - */ - - __kuser_get_tls: @ 0xffff0fe0 -- --#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) -- ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 --#else -- mrc p15, 0, r0, c13, c0, 3 @ read TLS register --#endif -+ ldr r0, [pc, #(16 - 8)] @ TLS set at 0xffff0ff0? -+ cmp r0, #0 @ assume hw TLS if not set -+ mrceq p15, 0, r0, c13, c0, 3 @ read TLS register - usr_ret lr - -- .rep 5 -+ .rep 3 - .word 0 @ pad up to __kuser_helper_version - .endr - -diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c -index c91c77b..de9d2dc 100644 ---- a/arch/arm/kernel/setup.c -+++ b/arch/arm/kernel/setup.c -@@ -269,6 +269,24 @@ static void __init cacheid_init(void) - extern struct proc_info_list *lookup_processor_type(unsigned int); - extern struct machine_desc *lookup_machine_type(unsigned int); - -+#ifdef CONFIG_CPU_V6 -+static void __init feat_v6_fixup(void) -+{ -+ int id = read_cpuid_id(); -+ -+ if (id & 0x000f0000 != 0x00070000) -+ return; -+ -+ /* HWCAP_TLS is available only on V6 r1p0 and later */ -+ if (((id >> 20) & 3) == 0) -+ elf_hwcap &= ~HWCAP_TLS; -+} -+#else -+static inline void feat_v6_fixup(void) -+{ -+} -+#endif -+ - static void __init setup_processor(void) - { - struct proc_info_list *list; -@@ -311,6 +329,8 @@ static void __init setup_processor(void) - elf_hwcap &= ~HWCAP_THUMB; - #endif - -+ feat_v6_fixup(); -+ - cacheid_init(); - cpu_proc_init(); - } -diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c -index 1621e53..bdffef5 100644 ---- a/arch/arm/kernel/traps.c -+++ b/arch/arm/kernel/traps.c -@@ -518,16 +518,19 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) - - case NR(set_tls): - thread->tp_value = regs->ARM_r0; --#if defined(CONFIG_HAS_TLS_REG) -- asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); --#elif !defined(CONFIG_TLS_REG_EMUL) -- /* -- * User space must never try to access this directly. -- * Expect your app to break eventually if you do so. -- * The user helper at 0xffff0fe0 must be used instead. -- * (see entry-armv.S for details) -- */ -- *((unsigned int *)0xffff0ff0) = regs->ARM_r0; -+#if !defined(CONFIG_TLS_REG_EMUL) -+ if (elf_hwcap & HWCAP_TLS) { -+ asm ("mcr p15, 0, %0, c13, c0, 3" -+ : : "r" (regs->ARM_r0)); -+ } else { -+ /* -+ * User space must never try to access this directly. -+ * Expect your app to break eventually if you do so. -+ * The user helper at 0xffff0fe0 must be used instead. -+ * (see entry-armv.S for details) -+ */ -+ *((unsigned int *)0xffff0ff0) = regs->ARM_r0; -+ } - #endif - return 0; - -diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index c4ed9f9..45e99c1 100644 ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -715,17 +715,6 @@ config TLS_REG_EMUL - a few prototypes like that in existence) and therefore access to - that required register must be emulated. - --config HAS_TLS_REG -- bool -- depends on !TLS_REG_EMUL -- default y if SMP || CPU_32v7 -- help -- This selects support for the CP15 thread register. -- It is defined to be available on some ARMv6 processors (including -- all SMP capable ARMv6's) or later processors. User space may -- assume directly accessing that register and always obtain the -- expected value only on ARMv7 and above. -- - config NEEDS_SYSCALL_FOR_CMPXCHG - bool - help -diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S -index 7a5337e..e10626a 100644 ---- a/arch/arm/mm/proc-v6.S -+++ b/arch/arm/mm/proc-v6.S -@@ -239,7 +239,8 @@ __v6_proc_info: - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA -+ /* See also feat_v6_fixup() for HWCAP_TLS */ -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS - .long cpu_v6_name - .long v6_processor_functions - .long v6wbi_tlb_fns -@@ -262,7 +263,8 @@ __pj4_v6_proc_info: - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ /* See also feat_v6_fixup() for HWCAP_TLS */ -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_pj4_name - .long v6_processor_functions - .long v6wbi_tlb_fns -diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S -index 7aaf88a..8071bcd 100644 ---- a/arch/arm/mm/proc-v7.S -+++ b/arch/arm/mm/proc-v7.S -@@ -344,7 +344,7 @@ __v7_proc_info: - b __v7_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_v7_name - .long v7_processor_functions - .long v7wbi_tlb_fns diff --git a/a/content_digest b/N1/content_digest index 55cfa43..9f017ad 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,13 +3,11 @@ "ref\020100317191114.GH2900@atomide.com\0" "ref\01268910826.15334.32.camel@e102109-lin.cambridge.arm.com\0" "ref\020100318170021.GN2900@atomide.com\0" - "From\0Tony Lindgren <tony@atomide.com>\0" + "From\0tony@atomide.com (Tony Lindgren)\0" "Subject\0[PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\0" "Date\0Thu, 18 Mar 2010 18:35:21 -0700\0" - "To\0Catalin Marinas <catalin.marinas@arm.com>\0" - "Cc\0linux-omap@vger.kernel.org" - " linux-arm-kernel@lists.infradead.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "* Tony Lindgren <tony@atomide.com> [100318 09:55]:\n" "> * Catalin Marinas <catalin.marinas@arm.com> [100318 04:10]:\n" @@ -50,204 +48,5 @@ "Regards,\n" "\n" Tony - "\01:2\0" - "fn\0arm-check-tls.patch\0" - "b\0" - ">From 81d4bf2481c4ef5fd80261605977b5f55e4515e4 Mon Sep 17 00:00:00 2001\n" - "From: Tony Lindgren <tony@atomide.com>\n" - "Date: Thu, 18 Mar 2010 12:02:43 -0700\n" - "Subject: [PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\n" - "\n" - "The TLS register is only available on V6 r1p0 and later.\n" - "Test for it and use it if available.\n" - "\n" - "Signed-off-by: Tony Lindgren <tony@atomide.com>\n" - "\n" - "diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h\n" - "index f7bd52b..c1062c3 100644\n" - "--- a/arch/arm/include/asm/hwcap.h\n" - "+++ b/arch/arm/include/asm/hwcap.h\n" - "@@ -19,6 +19,7 @@\n" - " #define HWCAP_NEON\t4096\n" - " #define HWCAP_VFPv3\t8192\n" - " #define HWCAP_VFPv3D16\t16384\n" - "+#define HWCAP_TLS\t32768\n" - " \n" - " #if defined(__KERNEL__) && !defined(__ASSEMBLY__)\n" - " /*\n" - "diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S\n" - "index 6c5cf36..5a5aac8 100644\n" - "--- a/arch/arm/kernel/entry-armv.S\n" - "+++ b/arch/arm/kernel/entry-armv.S\n" - "@@ -739,11 +739,13 @@ ENTRY(__switch_to)\n" - " #ifdef CONFIG_MMU\n" - " \tldr\tr6, [r2, #TI_CPU_DOMAIN]\n" - " #endif\n" - "-#if defined(CONFIG_HAS_TLS_REG)\n" - "-\tmcr\tp15, 0, r3, c13, c0, 3\t\t@ set TLS register\n" - "-#elif !defined(CONFIG_TLS_REG_EMUL)\n" - "-\tmov\tr4, #0xffff0fff\n" - "-\tstr\tr3, [r4, #-15]\t\t\t@ TLS val at 0xffff0ff0\n" - "+#if !defined(CONFIG_TLS_REG_EMUL)\n" - "+\tldr\tr4, =elf_hwcap\n" - "+\tldr\tr4, [r4, #0]\n" - "+\ttst\tr4, #HWCAP_TLS\t\t\t@ hardware with TLS?\n" - "+\tmcrne\tp15, 0, r3, c13, c0, 3\t\t@ set TLS register\n" - "+\tmoveq\tr4, #0xffff0fff\n" - "+\tstreq\tr3, [r4, #-15]\t\t\t@ TLS val at 0xffff0ff0\n" - " #endif\n" - " #ifdef CONFIG_MMU\n" - " \tmcr\tp15, 0, r6, c3, c0, 0\t\t@ Set domain register\n" - "@@ -1009,15 +1011,12 @@ kuser_cmpxchg_fixup:\n" - " */\n" - " \n" - " __kuser_get_tls:\t\t\t\t@ 0xffff0fe0\n" - "-\n" - "-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)\n" - "-\tldr\tr0, [pc, #(16 - 8)]\t\t@ TLS stored at 0xffff0ff0\n" - "-#else\n" - "-\tmrc\tp15, 0, r0, c13, c0, 3\t\t@ read TLS register\n" - "-#endif\n" - "+\tldr r0, [pc, #(16 - 8)]\t\t@ TLS set at 0xffff0ff0?\n" - "+\tcmp\tr0, #0\t\t\t\t@ assume hw TLS if not set\n" - "+\tmrceq\tp15, 0, r0, c13, c0, 3\t\t@ read TLS register\n" - " \tusr_ret\tlr\n" - " \n" - "-\t.rep\t5\n" - "+\t.rep\t3\n" - " \t.word\t0\t\t\t@ pad up to __kuser_helper_version\n" - " \t.endr\n" - " \n" - "diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c\n" - "index c91c77b..de9d2dc 100644\n" - "--- a/arch/arm/kernel/setup.c\n" - "+++ b/arch/arm/kernel/setup.c\n" - "@@ -269,6 +269,24 @@ static void __init cacheid_init(void)\n" - " extern struct proc_info_list *lookup_processor_type(unsigned int);\n" - " extern struct machine_desc *lookup_machine_type(unsigned int);\n" - " \n" - "+#ifdef CONFIG_CPU_V6\n" - "+static void __init feat_v6_fixup(void)\n" - "+{\n" - "+\tint id = read_cpuid_id();\n" - "+\n" - "+\tif (id & 0x000f0000 != 0x00070000)\n" - "+\t\treturn;\n" - "+\n" - "+\t/* HWCAP_TLS is available only on V6 r1p0 and later */\n" - "+\tif (((id >> 20) & 3) == 0)\n" - "+\t\telf_hwcap &= ~HWCAP_TLS;\n" - "+}\n" - "+#else\n" - "+static inline void feat_v6_fixup(void)\n" - "+{\n" - "+}\n" - "+#endif\n" - "+\n" - " static void __init setup_processor(void)\n" - " {\n" - " \tstruct proc_info_list *list;\n" - "@@ -311,6 +329,8 @@ static void __init setup_processor(void)\n" - " \telf_hwcap &= ~HWCAP_THUMB;\n" - " #endif\n" - " \n" - "+\tfeat_v6_fixup();\n" - "+\n" - " \tcacheid_init();\n" - " \tcpu_proc_init();\n" - " }\n" - "diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c\n" - "index 1621e53..bdffef5 100644\n" - "--- a/arch/arm/kernel/traps.c\n" - "+++ b/arch/arm/kernel/traps.c\n" - "@@ -518,16 +518,19 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)\n" - " \n" - " \tcase NR(set_tls):\n" - " \t\tthread->tp_value = regs->ARM_r0;\n" - "-#if defined(CONFIG_HAS_TLS_REG)\n" - "-\t\tasm (\"mcr p15, 0, %0, c13, c0, 3\" : : \"r\" (regs->ARM_r0) );\n" - "-#elif !defined(CONFIG_TLS_REG_EMUL)\n" - "-\t\t/*\n" - "-\t\t * User space must never try to access this directly.\n" - "-\t\t * Expect your app to break eventually if you do so.\n" - "-\t\t * The user helper at 0xffff0fe0 must be used instead.\n" - "-\t\t * (see entry-armv.S for details)\n" - "-\t\t */\n" - "-\t\t*((unsigned int *)0xffff0ff0) = regs->ARM_r0;\n" - "+#if !defined(CONFIG_TLS_REG_EMUL)\n" - "+\t\tif (elf_hwcap & HWCAP_TLS) {\n" - "+\t\t\tasm (\"mcr p15, 0, %0, c13, c0, 3\"\n" - "+\t\t\t\t: : \"r\" (regs->ARM_r0));\n" - "+\t\t} else {\n" - "+\t\t\t/*\n" - "+\t\t\t * User space must never try to access this directly.\n" - "+\t\t\t * Expect your app to break eventually if you do so.\n" - "+\t\t\t * The user helper at 0xffff0fe0 must be used instead.\n" - "+\t\t\t * (see entry-armv.S for details)\n" - "+\t\t\t */\n" - "+\t\t\t*((unsigned int *)0xffff0ff0) = regs->ARM_r0;\n" - "+\t\t}\n" - " #endif\n" - " \t\treturn 0;\n" - " \n" - "diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig\n" - "index c4ed9f9..45e99c1 100644\n" - "--- a/arch/arm/mm/Kconfig\n" - "+++ b/arch/arm/mm/Kconfig\n" - "@@ -715,17 +715,6 @@ config TLS_REG_EMUL\n" - " \t a few prototypes like that in existence) and therefore access to\n" - " \t that required register must be emulated.\n" - " \n" - "-config HAS_TLS_REG\n" - "-\tbool\n" - "-\tdepends on !TLS_REG_EMUL\n" - "-\tdefault y if SMP || CPU_32v7\n" - "-\thelp\n" - "-\t This selects support for the CP15 thread register.\n" - "-\t It is defined to be available on some ARMv6 processors (including\n" - "-\t all SMP capable ARMv6's) or later processors. User space may\n" - "-\t assume directly accessing that register and always obtain the\n" - "-\t expected value only on ARMv7 and above.\n" - "-\n" - " config NEEDS_SYSCALL_FOR_CMPXCHG\n" - " \tbool\n" - " \thelp\n" - "diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S\n" - "index 7a5337e..e10626a 100644\n" - "--- a/arch/arm/mm/proc-v6.S\n" - "+++ b/arch/arm/mm/proc-v6.S\n" - "@@ -239,7 +239,8 @@ __v6_proc_info:\n" - " \tb\t__v6_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA\n" - "+\t/* See also feat_v6_fixup() for HWCAP_TLS */\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS\n" - " \t.long\tcpu_v6_name\n" - " \t.long\tv6_processor_functions\n" - " \t.long\tv6wbi_tlb_fns\n" - "@@ -262,7 +263,8 @@ __pj4_v6_proc_info:\n" - " \tb\t__v6_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP\n" - "+\t/* See also feat_v6_fixup() for HWCAP_TLS */\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS\n" - " \t.long\tcpu_pj4_name\n" - " \t.long\tv6_processor_functions\n" - " \t.long\tv6wbi_tlb_fns\n" - "diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S\n" - "index 7aaf88a..8071bcd 100644\n" - "--- a/arch/arm/mm/proc-v7.S\n" - "+++ b/arch/arm/mm/proc-v7.S\n" - "@@ -344,7 +344,7 @@ __v7_proc_info:\n" - " \tb\t__v7_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS\n" - " \t.long\tcpu_v7_name\n" - " \t.long\tv7_processor_functions\n" - " \t.long\tv7wbi_tlb_fns" -d00dfd4615ca80c8f2030e2644766449fe635d7c5cb997ef0eb1fc2bd1f751d3 +d7a96dfb49319691293642fbc3494ed24770aa45252bb08c216785d76f91a2c9
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