From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nzs4A-0007Nk-Ui for qemu-devel@nongnu.org; Thu, 08 Apr 2010 09:46:42 -0400 Received: from [140.186.70.92] (port=32998 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nzs49-0007NO-N7 for qemu-devel@nongnu.org; Thu, 08 Apr 2010 09:46:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nzs48-00078A-7O for qemu-devel@nongnu.org; Thu, 08 Apr 2010 09:46:41 -0400 Received: from mx20.gnu.org ([199.232.41.8]:31268) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nzs48-000784-4w for qemu-devel@nongnu.org; Thu, 08 Apr 2010 09:46:40 -0400 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nzs47-0002L4-CJ for qemu-devel@nongnu.org; Thu, 08 Apr 2010 09:46:39 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instructions set Date: Thu, 8 Apr 2010 14:46:31 +0100 References: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> <1270662685-7379-7-git-send-email-aurelien@aurel32.net> In-Reply-To: <1270662685-7379-7-git-send-email-aurelien@aurel32.net> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Message-Id: <201004081446.32846.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andrzej Zaborowski , Aurelien Jarno > Use a set of #define to define the allowed ARM instructions, depending > on the __ARM_ARCH_*__ GCC defines. > > Signed-off-by: Aurelien Jarno > --- > tcg/arm/tcg-target.c | 27 ++++++++++++++++++++++++--- > 1 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c > index ee5f723..cae6385 100644 > --- a/tcg/arm/tcg-target.c > +++ b/tcg/arm/tcg-target.c > @@ -22,6 +22,27 @@ > * THE SOFTWARE. > */ > > +#if defined(__ARM_ARCH_5T__) || \ > + defined(__ARM_ARCH_5TE__) || \ > + defined(__ARM_ARCH_5TEJ__) || \ > + defined(__ARM_ARCH_6__) || \ > + defined(__ARM_ARCH_7A__) || \ > + defined(__ARM_ARCH_7__) > +# define USE_ARMV5_INSTRUCTIONS 1 > +#endif Would be better to avoid redundancy by reordering a bit and doing: #if defined(__ARM_ARCH_5T__) || \ defined(__ARM_ARCH_5TE__) || \ defined(__ARM_ARCH_5TEJ__) || \ defined(USE_ARMV6_INSTRUCTIONS) > +#if defined(__ARM_ARCH_6__) || \ > + defined(__ARM_ARCH_7A__) || \ > + defined(__ARM_ARCH_7__) > +# define USE_ARMV6_INSTRUCTIONS 1 > +#endif Likewise. > +#if defined(__ARM_ARCH_7A__) || \ > + defined(__ARM_ARCH_7__) > +# define USE_ARMV7_INSTRUCTIONS 1 > +#endif Missing check for __ARM_ARCH_7R__. Should probably also check 7M and 7EM, even though we don't currently generate Thumb code. Paul