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Date:   Tue, 13 Apr 2010 18:16:10 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc:     Wu Zhangjin <wuzhangjin@gmail.com>,
        David Daney <ddaney@caviumnetworks.com>,
        linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels
Message-ID: <20100413171610.GA16578@linux-mips.org>
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 <20100413073435.GA6371@alpha.franken.de>
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On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote:

> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
> > This patch have broken the support to the MIPS variants whose
> > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
> > in these MIPSs.
> 
> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
> about CPU we are talking ? And wouldn't it make for senso to have
> an extra define for the exception base then ?

C0_ebase's design was a short-sigthed only considering 32-bit processors.
So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
older.  So yes, there is a bug as I've verified by testing but the patch
is unfortunately incorrect.

  Ralf