From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] agp: use scratch page on memory remove and at GATT creation V2 Date: Tue, 20 Apr 2010 16:44:54 +0300 Message-ID: <20100420134454.GA6861@sci.fi> References: <1271766712-2032-1-git-send-email-glisse@freedesktop.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from filtteri2.pp.htv.fi (filtteri2.pp.htv.fi [213.243.153.185]) by gabe.freedesktop.org (Postfix) with ESMTP id 913F19EF5D for ; Tue, 20 Apr 2010 06:54:35 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1271766712-2032-1-git-send-email-glisse@freedesktop.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org To: glisse@freedesktop.org Cc: Jerome Glisse , stable , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Tue, Apr 20, 2010 at 02:31:52PM +0200, glisse@freedesktop.org wrote: > From: Jerome Glisse > = > Convert most AGP chipset to use scratch page as default entries. > This help avoiding GPU querying 0 address and trigger computer > fault. With KMS and memory manager we bind/unbind AGP memory > constantly and it seems that some GPU are still doing AGP > traffic even after GPU report being idle with the memory segment. > = > Tested (radeon GPU KMS + Xorg + compiz + glxgears + quake3) on : > - SIS 1039:0001 & 1039:0003 > - Intel 865 8086:2571 > = > Compile tested for other bridges > = > V2 enable scratch page on uninorth > = > Signed-off-by: Jerome Glisse > diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c > index 73dbf40..cf4dc4c 100644 > --- a/drivers/char/agp/amd-k7-agp.c > +++ b/drivers/char/agp/amd-k7-agp.c > @@ -178,6 +179,13 @@ static int amd_create_gatt_table(struct agp_bridge_d= ata *bridge) > readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ > } > = > + for (i =3D 0; i < value->num_entries; i++) { > + addr =3D (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; > + cur_gatt =3D GET_GATT(addr); > + writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); > + readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ > + } Isn't it enough to do a single PCI posting flush after writing all the entries? -- = Ville Syrj=E4l=E4 syrjala@sci.fi http://www.sci.fi/~syrjala/