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From: Robert Richter <robert.richter@amd.com>
To: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
	Ingo Molnar <mingo@elte.hu>, LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 11/12] perf, x86: implement AMD IBS event configuration
Date: Wed, 21 Apr 2010 18:58:43 +0200	[thread overview]
Message-ID: <20100421165843.GD6450@erda.amd.com> (raw)
In-Reply-To: <r2sbd4cb8901004210437i343850b4z94ca99b9ec0316b6@mail.gmail.com>

On 21.04.10 13:37:27, Stephane Eranian wrote:
> Why do you need model_spec, in addition to your special encoding?
> 
> >  /*
> > + * Model specific hardware events
> > + *
> > + * With the attr.model_spec bit set we can setup hardware events
> > + * others than generic performance counters. A special PMU 64 bit
> > + * config value can be passed through the perf_event interface. The
> > + * concept of PMU model-specific arguments was practiced already in
> > + * Perfmon2. The type of event (8 bits) is determinded from the config
> > + * value too, bit 32-39 are reserved for this.
> > + */
> Isn't the config field big enough to encode all the information you need?
> In the kernel, you could check bit 32-39 and based on host CPU determine
> whether it refers to IBS or is a bogus value. I am trying to figure out what
> model_spec buys you. I believe RAW does not mean the final value as
> accepted by HW but a value that must be interpreted by the model-specific
> code to eventually come up with a raw HW value. In the current code, the
> RAW value is never passed as is, it is assembled from various bits and
> pieces incl. attr.config of course.

The raw config value without the model_spec bit set would asume a
config value for a generic x86 counter. We could reuse also an unused
bit in this config value, but what if this bit will be somewhen used?
Or, it is available on one hw bot not another? So I found it much
cleaner to introduce this attribute flag that can be reused on other
architectures. Also, you will then have the freedom to implement model
specific generic events without using raw_config. As most pmu features
are setup with a 64 bit config value, I would prefer to have also the
encoding of the model specific event type outside of the config
value. A want to be close to the hw register layout without shifting
bits back and forth. This may also introduce trouble in the future if
we need all 64 bits.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center
email: robert.richter@amd.com


  reply	other threads:[~2010-04-21 16:58 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-13 20:23 [PATCH 00/12] perf: introduce model specific events and AMD IBS Robert Richter
2010-04-13 20:23 ` [PATCH 01/12] perf, x86: move perfctr init code to x86_setup_perfctr() Robert Richter
2010-05-07 18:42   ` [tip:perf/core] perf, x86: Move " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 02/12] perf, x86: moving x86_setup_perfctr() Robert Richter
2010-05-07 18:42   ` [tip:perf/core] perf, x86: Move x86_setup_perfctr() tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 03/12] perf, x86: call x86_setup_perfctr() from .hw_config() Robert Richter
2010-05-07 18:42   ` [tip:perf/core] perf, x86: Call " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 04/12] perf: introduce flag for model specific events Robert Richter
2010-04-13 20:23 ` [PATCH 05/12] perf, x86: pass enable bit mask to __x86_pmu_enable_event() Robert Richter
2010-05-07 18:43   ` [tip:perf/core] perf, x86: Pass " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 06/12] perf, x86: use weight instead of cmask in for_each_event_constraint() Robert Richter
2010-05-07 18:43   ` [tip:perf/core] perf, x86: Use " tip-bot for Robert Richter
2010-04-13 20:23 ` [PATCH 07/12] perf, x86: introduce bit range for special pmu events Robert Richter
2010-04-13 20:23 ` [PATCH 08/12] perf, x86: modify some code to allow the introduction of ibs events Robert Richter
2010-04-13 20:23 ` [PATCH 09/12] perf, x86: implement IBS feature detection Robert Richter
2010-04-13 20:23 ` [PATCH 10/12] perf, x86: setup NMI handler for IBS Robert Richter
2010-04-15 12:57   ` Peter Zijlstra
2010-04-15 13:11     ` Robert Richter
2010-04-19 16:04       ` Robert Richter
2010-04-13 20:23 ` [PATCH 11/12] perf, x86: implement AMD IBS event configuration Robert Richter
2010-04-19 13:46   ` Stephane Eranian
2010-04-20 10:31     ` Robert Richter
2010-04-20 16:05     ` Robert Richter
2010-04-21  8:47       ` Robert Richter
2010-04-21  9:02         ` Stephane Eranian
2010-04-21  9:21           ` Robert Richter
2010-04-21 10:54             ` Robert Richter
2010-04-21 11:37               ` Stephane Eranian
2010-04-21 16:58                 ` Robert Richter [this message]
2010-04-22 17:32                   ` Stephane Eranian
2010-05-11 13:57                 ` Robert Richter
2010-04-13 20:23 ` [PATCH 12/12] perf, x86: implement the ibs interrupt handler Robert Richter
2010-04-19 12:19   ` Stephane Eranian
2010-04-20 13:10     ` Robert Richter
2010-04-22 14:45     ` Robert Richter
2010-05-07 15:28     ` [PATCH] perf: fix raw sample size if no sampling data is attached Robert Richter
2010-05-07 15:41       ` Peter Zijlstra
2010-05-07 19:48       ` Robert Richter
2010-05-18 15:12     ` [RFC PATCH] perf: align raw sample data on 64-bit boundaries Robert Richter
2010-05-19  7:39       ` Frederic Weisbecker
2010-05-19  9:31         ` Robert Richter
2010-05-24 21:25           ` Frederic Weisbecker
2010-05-28 17:35             ` Robert Richter
2010-04-13 20:45 ` [osrc-patches] [PATCH 00/12] perf: introduce model specific events and AMD IBS Robert Richter
2010-04-14 12:31   ` Robert Richter
2010-04-15  7:41   ` Peter Zijlstra
2010-04-15  7:44 ` Peter Zijlstra
2010-04-15 15:16   ` Robert Richter
2010-04-21 12:11     ` Peter Zijlstra
2010-04-21 13:21       ` Stephane Eranian
2010-04-21 18:26         ` Robert Richter
2010-04-21 18:40           ` Stephane Eranian
2010-04-21 16:28       ` Robert Richter
2010-04-28 16:16 ` [osrc-patches] " Robert Richter
2010-05-04 14:18   ` Peter Zijlstra

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