From: Cyrill Gorcunov <gorcunov@gmail.com>
To: Jaswinder Singh Rajput <jaswinderlinux@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>, Lin Ming <ming.m.lin@intel.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Frederic Weisbecker <fweisbec@gmail.com>
Subject: Re: Performance Events hangs with Intel P4 system
Date: Fri, 14 May 2010 22:01:48 +0400 [thread overview]
Message-ID: <20100514180148.GE13509@lenovo> (raw)
In-Reply-To: <AANLkTinQL16caUSZnFFr4gs_vfT93mwkNTK7I_eShZvA@mail.gmail.com>
On Fri, May 14, 2010 at 11:18:52PM +0530, Jaswinder Singh Rajput wrote:
...
> Earlier I given the command 'ls' which was very small only 601636
> instructions so branches
> and branch-misses came up with <not counted>
>
> When I given a bigger command 'ls -lR /dev' with 10159428
> instructions, so I get branches and branch-misses count.
>
> Thanks,
> --
> Jaswinder Singh.
>
Jaswinder, could you give this patch a shot so that I will be
able to put your tested-by tag and send it upstream? (it's slightly
tuned from previous but should be same on bin level). This GP
issue need to be fixed before any other things.
-- Cyrill
---
arch/x86/kernel/cpu/perf_event_p4.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
Index: linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
=====================================================================
--- linux-2.6.git.orig/arch/x86/kernel/cpu/perf_event_p4.c
+++ linux-2.6.git/arch/x86/kernel/cpu/perf_event_p4.c
@@ -18,7 +18,7 @@
struct p4_event_bind {
unsigned int opcode; /* Event code and ESCR selector */
unsigned int escr_msr[2]; /* ESCR MSR for this event */
- unsigned char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */
+ char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on abscence */
};
struct p4_cache_event_bind {
@@ -747,11 +747,11 @@ static int p4_get_escr_idx(unsigned int
static int p4_next_cntr(int thread, unsigned long *used_mask,
struct p4_event_bind *bind)
{
- int i = 0, j;
+ int i, j;
for (i = 0; i < P4_CNTR_LIMIT; i++) {
- j = bind->cntr[thread][i++];
- if (j == -1 || !test_bit(j, used_mask))
+ j = bind->cntr[thread][i];
+ if (j != -1 && !test_bit(j, used_mask))
return j;
}
next prev parent reply other threads:[~2010-05-14 18:02 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-13 22:17 Performance Events hangs with Intel P4 system Jaswinder Singh Rajput
2010-05-14 3:19 ` Cyrill Gorcunov
2010-05-14 4:25 ` Jaswinder Singh Rajput
2010-05-14 4:29 ` Cyrill Gorcunov
2010-05-14 6:23 ` Cyrill Gorcunov
2010-05-14 7:52 ` Jaswinder Singh Rajput
2010-05-14 8:41 ` Cyrill Gorcunov
2010-05-14 10:04 ` Cyrill Gorcunov
2010-05-14 10:46 ` Cyrill Gorcunov
2010-05-14 10:56 ` Lin Ming
2010-05-14 11:56 ` Ingo Molnar
2010-05-14 12:07 ` Cyrill Gorcunov
2010-05-14 13:52 ` Cyrill Gorcunov
2010-05-14 14:52 ` Cyrill Gorcunov
2010-05-14 16:22 ` Jaswinder Singh Rajput
2010-05-14 16:28 ` Cyrill Gorcunov
2010-05-14 16:36 ` Jaswinder Singh Rajput
2010-05-14 16:40 ` Cyrill Gorcunov
2010-05-14 17:48 ` Jaswinder Singh Rajput
2010-05-14 18:01 ` Cyrill Gorcunov [this message]
2010-05-14 18:33 ` Jaswinder Singh Rajput
2010-05-14 17:30 ` Cyrill Gorcunov
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