From mboxrd@z Thu Jan 1 00:00:00 1970 From: Li Peng Subject: Re: [PATCH] drm/i915: Add CxSR support on Pineview DDR3 Date: Tue, 18 May 2010 18:24:23 +0800 Message-ID: <20100518102423.GA14910@pli1.bj.intel.com> References: <20100517140730.GA21744@pli1.bj.intel.com> <20100517092638.GB19057@zhen-devel.sh.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from orsmga101.jf.intel.com (mga06.intel.com [134.134.136.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AEF79EB29 for ; Mon, 17 May 2010 19:24:26 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20100517092638.GB19057@zhen-devel.sh.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Zhenyu Wang , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, May 17, 2010 at 05:26:38PM +0800, Zhenyu Wang wrote: > On 2010.05.17 22:07:30 +0800, Li Peng wrote: > > Pineview with DDR3 memory has different latencies to enable CxSR. > > This patch updates CxSR latency table to add Pineview DDR3 latency > > configuration. It also adds one flag "is_ddr3" for checking DDR3 > > setting in MCHBAR. > > > > This is not against drm-intel-next? which has commit d4294342f to > cleanup wm setup for pineview. > Thanks for the reminder. The patch is against mainline. I will rebase it to drm-intel-next. Peng > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827