From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org, agraf@suse.de
Subject: Re: [Qemu-devel] [PATCH 17/35] tcg-s390: Implement sign and zero-extension operations.
Date: Sat, 12 Jun 2010 14:32:46 +0200 [thread overview]
Message-ID: <20100612123246.GN3008@ohm.aurel32.net> (raw)
In-Reply-To: <1275678883-7082-18-git-send-email-rth@twiddle.net>
On Fri, Jun 04, 2010 at 12:14:25PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/s390/tcg-target.c | 164 ++++++++++++++++++++++++++++++++++++++++++++-----
> tcg/s390/tcg-target.h | 20 +++---
> 2 files changed, 158 insertions(+), 26 deletions(-)
This patch looks fine.
> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 71e017a..42e3224 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -78,10 +78,14 @@ typedef enum S390Opcode {
> RRE_DLR = 0xb997,
> RRE_DSGFR = 0xb91d,
> RRE_DSGR = 0xb90d,
> + RRE_LGBR = 0xb906,
> RRE_LCGR = 0xb903,
> RRE_LGFR = 0xb914,
> + RRE_LGHR = 0xb907,
> RRE_LGR = 0xb904,
> + RRE_LLGCR = 0xb984,
> RRE_LLGFR = 0xb916,
> + RRE_LLGHR = 0xb985,
> RRE_MSGR = 0xb90c,
> RRE_MSR = 0xb252,
> RRE_NGR = 0xb980,
> @@ -117,11 +121,9 @@ typedef enum S390Opcode {
> RXY_LGF = 0xe314,
> RXY_LGH = 0xe315,
> RXY_LHY = 0xe378,
> - RXY_LLC = 0xe394,
> RXY_LLGC = 0xe390,
> RXY_LLGF = 0xe316,
> RXY_LLGH = 0xe391,
> - RXY_LLH = 0xe395,
> RXY_LMG = 0xeb04,
> RXY_LRV = 0xe31e,
> RXY_LRVG = 0xe30f,
> @@ -553,6 +555,96 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
> }
> }
>
> +static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> +{
> + if (facilities & FACILITY_EXT_IMM) {
> + tcg_out_insn(s, RRE, LGBR, dest, src);
> + return;
> + }
> +
> + if (type == TCG_TYPE_I32) {
> + if (dest == src) {
> + tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
> + } else {
> + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
> + }
> + tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
> + } else {
> + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
> + tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
> + }
> +}
> +
> +static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> +{
> + if (facilities & FACILITY_EXT_IMM) {
> + tcg_out_insn(s, RRE, LLGCR, dest, src);
> + return;
> + }
> +
> + if (dest == src) {
> + tcg_out_movi(s, type, TCG_TMP0, 0xff);
> + src = TCG_TMP0;
> + } else {
> + tcg_out_movi(s, type, dest, 0xff);
> + }
> + if (type == TCG_TYPE_I32) {
> + tcg_out_insn(s, RR, NR, dest, src);
> + } else {
> + tcg_out_insn(s, RRE, NGR, dest, src);
> + }
> +}
> +
> +static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> +{
> + if (facilities & FACILITY_EXT_IMM) {
> + tcg_out_insn(s, RRE, LGHR, dest, src);
> + return;
> + }
> +
> + if (type == TCG_TYPE_I32) {
> + if (dest == src) {
> + tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
> + } else {
> + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
> + }
> + tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
> + } else {
> + tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
> + tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
> + }
> +}
> +
> +static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
> +{
> + if (facilities & FACILITY_EXT_IMM) {
> + tcg_out_insn(s, RRE, LLGHR, dest, src);
> + return;
> + }
> +
> + if (dest == src) {
> + tcg_out_movi(s, type, TCG_TMP0, 0xffff);
> + src = TCG_TMP0;
> + } else {
> + tcg_out_movi(s, type, dest, 0xffff);
> + }
> + if (type == TCG_TYPE_I32) {
> + tcg_out_insn(s, RR, NR, dest, src);
> + } else {
> + tcg_out_insn(s, RRE, NGR, dest, src);
> + }
> +}
> +
> +static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
> +{
> + tcg_out_insn(s, RRE, LGFR, dest, src);
> +}
> +
> +static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
> +{
> + tcg_out_insn(s, RRE, LLGFR, dest, src);
> +}
> +
> static void tgen32_cmp(TCGContext *s, TCGCond c, TCGReg r1, TCGReg r2)
> {
> if (c > TCG_COND_GT) {
> @@ -643,8 +735,8 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg,
> }
>
> #if TARGET_LONG_BITS == 32
> - tcg_out_insn(s, RRE, LLGFR, arg1, addr_reg);
> - tcg_out_insn(s, RRE, LLGFR, arg0, addr_reg);
> + tgen_ext32u(s, arg1, addr_reg);
> + tgen_ext32u(s, arg0, addr_reg);
> #else
> tcg_out_mov(s, arg1, addr_reg);
> tcg_out_mov(s, arg0, addr_reg);
> @@ -681,7 +773,7 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg,
>
> /* call load/store helper */
> #if TARGET_LONG_BITS == 32
> - tcg_out_insn(s, RRE, LLGFR, arg0, addr_reg);
> + tgen_ext32u(s, arg0, addr_reg);
> #else
> tcg_out_mov(s, arg0, addr_reg);
> #endif
> @@ -697,15 +789,13 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg,
> /* sign extension */
> switch (opc) {
> case LD_INT8:
> - tcg_out_insn(s, RSY, SLLG, data_reg, arg0, TCG_REG_NONE, 56);
> - tcg_out_insn(s, RSY, SRAG, data_reg, data_reg, TCG_REG_NONE, 56);
> + tgen_ext8s(s, TCG_TYPE_I64, data_reg, arg0);
> break;
> case LD_INT16:
> - tcg_out_insn(s, RSY, SLLG, data_reg, arg0, TCG_REG_NONE, 48);
> - tcg_out_insn(s, RSY, SRAG, data_reg, data_reg, TCG_REG_NONE, 48);
> + tgen_ext16s(s, TCG_TYPE_I64, data_reg, arg0);
> break;
> case LD_INT32:
> - tcg_out_insn(s, RRE, LGFR, data_reg, arg0);
> + tgen_ext32s(s, data_reg, arg0);
> break;
> default:
> /* unsigned -> just copy */
> @@ -803,8 +893,7 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
> #else
> /* swapped unsigned halfword load with upper bits zeroed */
> tcg_out_insn(s, RXY, LRVH, data_reg, arg0, 0, 0);
> - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 0xffffL);
> - tcg_out_insn(s, RRE, NGR, data_reg, TCG_TMP0);
> + tgen_ext16u(s, TCG_TYPE_I64, data_reg, data_reg);
> #endif
> break;
> case LD_INT16:
> @@ -813,8 +902,7 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
> #else
> /* swapped sign-extended halfword load */
> tcg_out_insn(s, RXY, LRVH, data_reg, arg0, 0, 0);
> - tcg_out_insn(s, RSY, SLLG, data_reg, data_reg, TCG_REG_NONE, 48);
> - tcg_out_insn(s, RSY, SRAG, data_reg, data_reg, TCG_REG_NONE, 48);
> + tgen_ext16s(s, TCG_TYPE_I64, data_reg, data_reg);
> #endif
> break;
> case LD_UINT32:
> @@ -823,7 +911,7 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
> #else
> /* swapped unsigned int load with upper bits zeroed */
> tcg_out_insn(s, RXY, LRV, data_reg, arg0, 0, 0);
> - tcg_out_insn(s, RRE, LLGFR, data_reg, data_reg);
> + tgen_ext32u(s, data_reg, data_reg);
> #endif
> break;
> case LD_INT32:
> @@ -832,7 +920,7 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc)
> #else
> /* swapped sign-extended int load */
> tcg_out_insn(s, RXY, LRV, data_reg, arg0, 0, 0);
> - tcg_out_insn(s, RRE, LGFR, data_reg, data_reg);
> + tgen_ext32s(s, data_reg, data_reg);
> #endif
> break;
> case LD_UINT64:
> @@ -1111,6 +1199,38 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> op = RSY_SRAG;
> goto do_shift64;
>
> + case INDEX_op_ext8s_i32:
> + tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
> + break;
> + case INDEX_op_ext8s_i64:
> + tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
> + break;
> + case INDEX_op_ext16s_i32:
> + tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
> + break;
> + case INDEX_op_ext16s_i64:
> + tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
> + break;
> + case INDEX_op_ext32s_i64:
> + tgen_ext32s(s, args[0], args[1]);
> + break;
> +
> + case INDEX_op_ext8u_i32:
> + tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
> + break;
> + case INDEX_op_ext8u_i64:
> + tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
> + break;
> + case INDEX_op_ext16u_i32:
> + tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
> + break;
> + case INDEX_op_ext16u_i64:
> + tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
> + break;
> + case INDEX_op_ext32u_i64:
> + tgen_ext32u(s, args[0], args[1]);
> + break;
> +
> case INDEX_op_br:
> tgen_branch(s, S390_CC_ALWAYS, args[0]);
> break;
> @@ -1228,6 +1348,11 @@ static const TCGTargetOpDef s390_op_defs[] = {
> { INDEX_op_shr_i32, { "r", "0", "Ri" } },
> { INDEX_op_sar_i32, { "r", "0", "Ri" } },
>
> + { INDEX_op_ext8s_i32, { "r", "r" } },
> + { INDEX_op_ext8u_i32, { "r", "r" } },
> + { INDEX_op_ext16s_i32, { "r", "r" } },
> + { INDEX_op_ext16u_i32, { "r", "r" } },
> +
> { INDEX_op_brcond_i32, { "r", "r" } },
> { INDEX_op_setcond_i32, { "r", "r", "r" } },
>
> @@ -1278,6 +1403,13 @@ static const TCGTargetOpDef s390_op_defs[] = {
> { INDEX_op_shr_i64, { "r", "r", "Ri" } },
> { INDEX_op_sar_i64, { "r", "r", "Ri" } },
>
> + { INDEX_op_ext8s_i64, { "r", "r" } },
> + { INDEX_op_ext8u_i64, { "r", "r" } },
> + { INDEX_op_ext16s_i64, { "r", "r" } },
> + { INDEX_op_ext16u_i64, { "r", "r" } },
> + { INDEX_op_ext32s_i64, { "r", "r" } },
> + { INDEX_op_ext32u_i64, { "r", "r" } },
> +
> { INDEX_op_brcond_i64, { "r", "r" } },
> { INDEX_op_setcond_i64, { "r", "r", "r" } },
> #endif
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 26dafae..570c832 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -50,10 +50,10 @@ typedef enum TCGReg {
> /* optional instructions */
> #define TCG_TARGET_HAS_div2_i32
> // #define TCG_TARGET_HAS_rot_i32
> -// #define TCG_TARGET_HAS_ext8s_i32
> -// #define TCG_TARGET_HAS_ext16s_i32
> -// #define TCG_TARGET_HAS_ext8u_i32
> -// #define TCG_TARGET_HAS_ext16u_i32
> +#define TCG_TARGET_HAS_ext8s_i32
> +#define TCG_TARGET_HAS_ext16s_i32
> +#define TCG_TARGET_HAS_ext8u_i32
> +#define TCG_TARGET_HAS_ext16u_i32
> // #define TCG_TARGET_HAS_bswap16_i32
> // #define TCG_TARGET_HAS_bswap32_i32
> // #define TCG_TARGET_HAS_not_i32
> @@ -66,12 +66,12 @@ typedef enum TCGReg {
>
> #define TCG_TARGET_HAS_div2_i64
> // #define TCG_TARGET_HAS_rot_i64
> -// #define TCG_TARGET_HAS_ext8s_i64
> -// #define TCG_TARGET_HAS_ext16s_i64
> -// #define TCG_TARGET_HAS_ext32s_i64
> -// #define TCG_TARGET_HAS_ext8u_i64
> -// #define TCG_TARGET_HAS_ext16u_i64
> -// #define TCG_TARGET_HAS_ext32u_i64
> +#define TCG_TARGET_HAS_ext8s_i64
> +#define TCG_TARGET_HAS_ext16s_i64
> +#define TCG_TARGET_HAS_ext32s_i64
> +#define TCG_TARGET_HAS_ext8u_i64
> +#define TCG_TARGET_HAS_ext16u_i64
> +#define TCG_TARGET_HAS_ext32u_i64
> // #define TCG_TARGET_HAS_bswap16_i64
> // #define TCG_TARGET_HAS_bswap32_i64
> // #define TCG_TARGET_HAS_bswap64_i64
> --
> 1.7.0.1
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2010-06-12 14:14 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-04 19:14 [Qemu-devel] [PATCH 00/35] S390 TCG target, version 2 Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 01/35] tcg-s390: Adjust compilation flags Richard Henderson
2010-06-09 22:53 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 02/35] s390x: Avoid _llseek Richard Henderson
2010-06-09 22:54 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 03/35] s390x: Don't use a linker script for user-only Richard Henderson
2010-06-09 22:54 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 04/35] tcg-s390: Compute is_write in cpu_signal_handler Richard Henderson
2010-06-09 22:54 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 05/35] tcg-s390: Icache flush is a no-op Richard Henderson
2010-06-09 22:55 ` Aurelien Jarno
2010-06-10 22:04 ` Richard Henderson
2010-06-11 6:46 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 06/35] tcg-s390: Allocate the code_gen_buffer near the main program Richard Henderson
2010-06-09 22:59 ` Aurelien Jarno
2010-06-10 22:05 ` Richard Henderson
2010-06-11 7:31 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 07/35] tcg: Optionally sign-extend 32-bit arguments for 64-bit host Richard Henderson
2010-06-10 10:22 ` Aurelien Jarno
2010-06-10 22:08 ` Richard Henderson
2010-06-14 22:20 ` Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 08/35] s390: Update disassembler to the last GPLv2 from binutils Richard Henderson
2010-06-09 22:47 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 09/35] s390: Disassemble some general-instruction-extension insns Richard Henderson
2010-06-09 22:47 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 10/35] tcg-s390: New TCG target Richard Henderson
2010-06-10 10:24 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 11/35] tcg-s390: Tidy unimplemented opcodes Richard Henderson
2010-06-10 10:24 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 12/35] tcg-s390: Define TCG_TMP0 Richard Henderson
2010-06-10 10:25 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 13/35] tcg-s390: Tidy regset initialization; use R14 as temporary Richard Henderson
2010-06-10 10:26 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 14/35] tcg-s390: Rearrange register allocation order Richard Henderson
2010-06-10 10:26 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 15/35] tcg-s390: Query instruction extensions that are installed Richard Henderson
2010-06-10 10:28 ` Aurelien Jarno
2010-06-10 22:19 ` Richard Henderson
2010-06-11 8:06 ` Aurelien Jarno
2010-06-11 13:07 ` Richard Henderson
2010-06-12 11:57 ` Aurelien Jarno
2010-06-11 13:13 ` Richard Henderson
2010-06-13 10:49 ` Aurelien Jarno
2010-06-13 16:02 ` Richard Henderson
2010-06-13 16:44 ` Aurelien Jarno
2010-06-13 22:23 ` Alexander Graf
2010-06-14 16:20 ` Richard Henderson
2010-06-14 17:39 ` Alexander Graf
2010-06-04 19:14 ` [Qemu-devel] [PATCH 16/35] tcg-s390: Re-implement tcg_out_movi Richard Henderson
2010-06-12 12:04 ` Aurelien Jarno
2010-06-13 23:19 ` Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 17/35] tcg-s390: Implement sign and zero-extension operations Richard Henderson
2010-06-12 12:32 ` Aurelien Jarno [this message]
2010-06-04 19:14 ` [Qemu-devel] [PATCH 18/35] tcg-s390: Implement bswap operations Richard Henderson
2010-06-12 12:32 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 19/35] tcg-s390: Implement rotates Richard Henderson
2010-06-12 12:33 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 20/35] tcg-s390: Use LOAD COMPLIMENT for negate Richard Henderson
2010-06-12 12:33 ` Aurelien Jarno
2010-06-04 19:14 ` [Qemu-devel] [PATCH 21/35] tcg-s390: Use the ADD IMMEDIATE instructions Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 22/35] tcg-s390: Use the AND " Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 23/35] tcg-s390: Use the OR " Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 24/35] tcg-s390: Use the XOR " Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 25/35] tcg-s390: Use the MULTIPLY " Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 26/35] tcg-s390: Tidy goto_tb Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 27/35] tcg-s390: Rearrange qemu_ld/st to avoid register copy Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 28/35] tcg-s390: Tidy tcg_prepare_qemu_ldst Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 29/35] tcg-s390: Tidy user qemu_ld/st Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 30/35] tcg-s390: Implement GUEST_BASE Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 31/35] tcg-s390: Use 16-bit branches for forward jumps Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 32/35] tcg-s390: Use the LOAD AND TEST instruction for compares Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 33/35] tcg-s390: Use the COMPARE IMMEDIATE instrucions " Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 34/35] tcg-s390: Use COMPARE AND BRANCH instructions Richard Henderson
2010-06-04 19:14 ` [Qemu-devel] [PATCH 35/35] tcg-s390: Enable compile in 32-bit mode Richard Henderson
2010-06-08 13:11 ` [Qemu-devel] Re: [PATCH 00/35] S390 TCG target, version 2 Alexander Graf
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