diff for duplicates of <20100702103744.GJ6632@atomide.com> diff --git a/a/1.txt b/N1/1.txt index 88d3b94..f3193cf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -20,3 +20,10 @@ I like that too. Updated patch below. Tony +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: arm-tls-v7.patch +Type: text/x-diff +Size: 8749 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20100702/39043301/attachment.bin> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index ec1bfdf..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,2 +0,0 @@ -Content-Type: text/x-diff; charset=us-ascii -Content-Disposition: inline; filename="arm-tls-v7.patch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 406f866..0000000 --- a/a/2.txt +++ /dev/null @@ -1,296 +0,0 @@ -From: Tony Lindgren <tony@atomide.com> -Date: Fri, 2 Jul 2010 11:33:31 +0300 -Subject: [PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6 - -The TLS register is only available on ARM1136 r1p0 and later. -Set HWCAP_TLS flags if hardware TLS is available and test for -it if CONFIG_CPU_32v6K is not set for V6. - -Note that we set the TLS instruction in __kuser_get_tls -dynamically as suggested by Jamie Lokier <jamie@shareable.org>. - -Also the __switch_to code is optimized out in most cases as -suggested by Nicolas Pitre <nico@fluxnic.net>. - -Signed-off-by: Tony Lindgren <tony@atomide.com> -Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> - -diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h -index f7bd52b..c1062c3 100644 ---- a/arch/arm/include/asm/hwcap.h -+++ b/arch/arm/include/asm/hwcap.h -@@ -19,6 +19,7 @@ - #define HWCAP_NEON 4096 - #define HWCAP_VFPv3 8192 - #define HWCAP_VFPv3D16 16384 -+#define HWCAP_TLS 32768 - - #if defined(__KERNEL__) && !defined(__ASSEMBLY__) - /* -diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h -new file mode 100644 -index 0000000..e71d6ff ---- /dev/null -+++ b/arch/arm/include/asm/tls.h -@@ -0,0 +1,46 @@ -+#ifndef __ASMARM_TLS_H -+#define __ASMARM_TLS_H -+ -+#ifdef __ASSEMBLY__ -+ .macro set_tls_none, tp, tmp1, tmp2 -+ .endm -+ -+ .macro set_tls_v6k, tp, tmp1, tmp2 -+ mcr p15, 0, \tp, c13, c0, 3 @ set TLS register -+ .endm -+ -+ .macro set_tls_v6, tp, tmp1, tmp2 -+ ldr \tmp1, =elf_hwcap -+ ldr \tmp1, [\tmp1, #0] -+ mov \tmp2, #0xffff0fff -+ tst \tmp1, #HWCAP_TLS @ hardware TLS available? -+ mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register -+ streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 -+ .endm -+ -+ .macro set_tls_software, tp, tmp1, tmp2 -+ mov \tmp1, #0xffff0fff -+ str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 -+ .endm -+#endif -+ -+#ifdef CONFIG_TLS_REG_EMUL -+#define tls_emu 1 -+#define has_tls_reg 1 -+#define set_tls set_tls_none -+#elif __LINUX_ARM_ARCH__ >= 7 || \ -+ (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) -+#define tls_emu 0 -+#define has_tls_reg 1 -+#define set_tls set_tls_v6k -+#elif __LINUX_ARM_ARCH__ == 6 -+#define tls_emu 0 -+#define has_tls_reg (elf_hwcap & HWCAP_TLS) -+#define set_tls set_tls_v6 -+#else -+#define tls_emu 0 -+#define has_tls_reg 0 -+#define set_tls set_tls_software -+#endif -+ -+#endif /* __ASMARM_TLS_H */ -diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S -index 7ee48e7..a6cfb17 100644 ---- a/arch/arm/kernel/entry-armv.S -+++ b/arch/arm/kernel/entry-armv.S -@@ -22,6 +22,7 @@ - #include <asm/thread_notify.h> - #include <asm/unwind.h> - #include <asm/unistd.h> -+#include <asm/tls.h> - - #include "entry-header.S" - -@@ -739,12 +740,7 @@ ENTRY(__switch_to) - #ifdef CONFIG_MMU - ldr r6, [r2, #TI_CPU_DOMAIN] - #endif --#if defined(CONFIG_HAS_TLS_REG) -- mcr p15, 0, r3, c13, c0, 3 @ set TLS register --#elif !defined(CONFIG_TLS_REG_EMUL) -- mov r4, #0xffff0fff -- str r3, [r4, #-15] @ TLS val at 0xffff0ff0 --#endif -+ set_tls r3, r4, r5 - #ifdef CONFIG_MMU - mcr p15, 0, r6, c3, c0, 0 @ Set domain register - #endif -@@ -1009,17 +1005,12 @@ kuser_cmpxchg_fixup: - */ - - __kuser_get_tls: @ 0xffff0fe0 -- --#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) -- ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 --#else -- mrc p15, 0, r0, c13, c0, 3 @ read TLS register --#endif -+ ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init - usr_ret lr -- -- .rep 5 -- .word 0 @ pad up to __kuser_helper_version -- .endr -+ mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code -+ .rep 4 -+ .word 0 @ 0xffff0ff0 software TLS value, then -+ .endr @ pad up to __kuser_helper_version - - /* - * Reference declaration: -diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c -index 122d999..73921f1 100644 ---- a/arch/arm/kernel/setup.c -+++ b/arch/arm/kernel/setup.c -@@ -269,6 +269,21 @@ static void __init cacheid_init(void) - extern struct proc_info_list *lookup_processor_type(unsigned int); - extern struct machine_desc *lookup_machine_type(unsigned int); - -+static void __init feat_v6_fixup(void) -+{ -+ int id = read_cpuid_id(); -+ -+ if ((id & 0xff0f0000) != 0x41070000) -+ return; -+ -+ /* -+ * HWCAP_TLS is available only on 1136 r1p0 and later, -+ * see also kuser_get_tls_init. -+ */ -+ if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0)) -+ elf_hwcap &= ~HWCAP_TLS; -+} -+ - static void __init setup_processor(void) - { - struct proc_info_list *list; -@@ -311,6 +326,8 @@ static void __init setup_processor(void) - elf_hwcap &= ~HWCAP_THUMB; - #endif - -+ feat_v6_fixup(); -+ - cacheid_init(); - cpu_proc_init(); - } -diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c -index 1621e53..cda78d5 100644 ---- a/arch/arm/kernel/traps.c -+++ b/arch/arm/kernel/traps.c -@@ -30,6 +30,7 @@ - #include <asm/unistd.h> - #include <asm/traps.h> - #include <asm/unwind.h> -+#include <asm/tls.h> - - #include "ptrace.h" - #include "signal.h" -@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) - - case NR(set_tls): - thread->tp_value = regs->ARM_r0; --#if defined(CONFIG_HAS_TLS_REG) -- asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) ); --#elif !defined(CONFIG_TLS_REG_EMUL) -- /* -- * User space must never try to access this directly. -- * Expect your app to break eventually if you do so. -- * The user helper at 0xffff0fe0 must be used instead. -- * (see entry-armv.S for details) -- */ -- *((unsigned int *)0xffff0ff0) = regs->ARM_r0; --#endif -+ if (tls_emu) -+ return 0; -+ if (has_tls_reg) { -+ asm ("mcr p15, 0, %0, c13, c0, 3" -+ : : "r" (regs->ARM_r0)); -+ } else { -+ /* -+ * User space must never try to access this directly. -+ * Expect your app to break eventually if you do so. -+ * The user helper at 0xffff0fe0 must be used instead. -+ * (see entry-armv.S for details) -+ */ -+ *((unsigned int *)0xffff0ff0) = regs->ARM_r0; -+ } - return 0; - - #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG -@@ -743,6 +747,16 @@ void __init trap_init(void) - return; - } - -+static void __init kuser_get_tls_init(unsigned long vectors) -+{ -+ /* -+ * vectors + 0xfe0 = __kuser_get_tls -+ * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8 -+ */ -+ if (tls_emu || has_tls_reg) -+ memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4); -+} -+ - void __init early_trap_init(void) - { - unsigned long vectors = CONFIG_VECTORS_BASE; -@@ -761,6 +775,11 @@ void __init early_trap_init(void) - memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz); - - /* -+ * Do processor specific fixups for the kuser helpers -+ */ -+ kuser_get_tls_init(vectors); -+ -+ /* - * Copy signal return handlers into the vector page, and - * set sigreturn to be a pointer to these. - */ -diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index 346ae14..71d5d5e 100644 ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -717,17 +717,6 @@ config TLS_REG_EMUL - a few prototypes like that in existence) and therefore access to - that required register must be emulated. - --config HAS_TLS_REG -- bool -- depends on !TLS_REG_EMUL -- default y if SMP || CPU_32v7 -- help -- This selects support for the CP15 thread register. -- It is defined to be available on some ARMv6 processors (including -- all SMP capable ARMv6's) or later processors. User space may -- assume directly accessing that register and always obtain the -- expected value only on ARMv7 and above. -- - config NEEDS_SYSCALL_FOR_CMPXCHG - bool - help -diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S -index 7a5337e..2f5a3c2 100644 ---- a/arch/arm/mm/proc-v6.S -+++ b/arch/arm/mm/proc-v6.S -@@ -239,7 +239,8 @@ __v6_proc_info: - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA -+ /* See also feat_v6_fixup() for HWCAP_TLS */ -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS - .long cpu_v6_name - .long v6_processor_functions - .long v6wbi_tlb_fns -@@ -262,7 +263,7 @@ __pj4_v6_proc_info: - b __v6_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_pj4_name - .long v6_processor_functions - .long v6wbi_tlb_fns -diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S -index 7aaf88a..8071bcd 100644 ---- a/arch/arm/mm/proc-v7.S -+++ b/arch/arm/mm/proc-v7.S -@@ -344,7 +344,7 @@ __v7_proc_info: - b __v7_setup - .long cpu_arch_name - .long cpu_elf_name -- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP -+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS - .long cpu_v7_name - .long v7_processor_functions - .long v7wbi_tlb_fns diff --git a/a/content_digest b/N1/content_digest index c961a94..5e5087a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -8,14 +8,11 @@ "ref\020100701092510.GH2822@atomide.com\0" "ref\020100701174051.GA8786@shareable.org\0" "ref\0alpine.LFD.2.00.1007012226170.26524@xanadu.home\0" - "From\0Tony Lindgren <tony@atomide.com>\0" - "Subject\0Re: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\0" + "From\0tony@atomide.com (Tony Lindgren)\0" + "Subject\0[PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\0" "Date\0Fri, 2 Jul 2010 13:37:46 +0300\0" - "To\0Nicolas Pitre <nico@fluxnic.net>\0" - "Cc\0Jamie Lokier <jamie@shareable.org>" - linux-omap@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "* Nicolas Pitre <nico@fluxnic.net> [100702 05:31]:\n" "> On Thu, 1 Jul 2010, Jamie Lokier wrote:\n" @@ -38,305 +35,13 @@ "\n" "I like that too. Updated patch below.\n" "\n" - Tony - "\01:2\0" - "fn\0arm-tls-v7.patch\0" - "b\0" - "From: Tony Lindgren <tony@atomide.com>\n" - "Date: Fri, 2 Jul 2010 11:33:31 +0300\n" - "Subject: [PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\n" - "\n" - "The TLS register is only available on ARM1136 r1p0 and later.\n" - "Set HWCAP_TLS flags if hardware TLS is available and test for\n" - "it if CONFIG_CPU_32v6K is not set for V6.\n" - "\n" - "Note that we set the TLS instruction in __kuser_get_tls\n" - "dynamically as suggested by Jamie Lokier <jamie@shareable.org>.\n" - "\n" - "Also the __switch_to code is optimized out in most cases as\n" - "suggested by Nicolas Pitre <nico@fluxnic.net>.\n" - "\n" - "Signed-off-by: Tony Lindgren <tony@atomide.com>\n" - "Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>\n" - "\n" - "diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h\n" - "index f7bd52b..c1062c3 100644\n" - "--- a/arch/arm/include/asm/hwcap.h\n" - "+++ b/arch/arm/include/asm/hwcap.h\n" - "@@ -19,6 +19,7 @@\n" - " #define HWCAP_NEON\t4096\n" - " #define HWCAP_VFPv3\t8192\n" - " #define HWCAP_VFPv3D16\t16384\n" - "+#define HWCAP_TLS\t32768\n" - " \n" - " #if defined(__KERNEL__) && !defined(__ASSEMBLY__)\n" - " /*\n" - "diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h\n" - "new file mode 100644\n" - "index 0000000..e71d6ff\n" - "--- /dev/null\n" - "+++ b/arch/arm/include/asm/tls.h\n" - "@@ -0,0 +1,46 @@\n" - "+#ifndef __ASMARM_TLS_H\n" - "+#define __ASMARM_TLS_H\n" - "+\n" - "+#ifdef __ASSEMBLY__\n" - "+\t.macro set_tls_none, tp, tmp1, tmp2\n" - "+\t.endm\n" - "+\n" - "+\t.macro set_tls_v6k, tp, tmp1, tmp2\n" - "+\tmcr\tp15, 0, \\tp, c13, c0, 3\t\t@ set TLS register\n" - "+\t.endm\n" - "+\n" - "+\t.macro set_tls_v6, tp, tmp1, tmp2\n" - "+\tldr\t\\tmp1, =elf_hwcap\n" - "+\tldr\t\\tmp1, [\\tmp1, #0]\n" - "+\tmov\t\\tmp2, #0xffff0fff\n" - "+\ttst\t\\tmp1, #HWCAP_TLS\t\t@ hardware TLS available?\n" - "+\tmcrne\tp15, 0, \\tp, c13, c0, 3\t\t@ yes, set TLS register\n" - "+\tstreq\t\\tp, [\\tmp2, #-15]\t\t@ set TLS value at 0xffff0ff0\n" - "+\t.endm\n" - "+\n" - "+\t.macro set_tls_software, tp, tmp1, tmp2\n" - "+\tmov\t\\tmp1, #0xffff0fff\n" - "+\tstr\t\\tp, [\\tmp1, #-15]\t\t@ set TLS value at 0xffff0ff0\n" - "+\t.endm\n" - "+#endif\n" - "+\n" - "+#ifdef CONFIG_TLS_REG_EMUL\n" - "+#define tls_emu\t\t1\n" - "+#define has_tls_reg\t\t1\n" - "+#define set_tls\t\tset_tls_none\n" - "+#elif __LINUX_ARM_ARCH__ >= 7 ||\t\t\t\t\t\\\n" - "+\t(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))\n" - "+#define tls_emu\t\t0\n" - "+#define has_tls_reg\t\t1\n" - "+#define set_tls\t\tset_tls_v6k\n" - "+#elif __LINUX_ARM_ARCH__ == 6\n" - "+#define tls_emu\t\t0\n" - "+#define has_tls_reg\t\t(elf_hwcap & HWCAP_TLS)\n" - "+#define set_tls\t\tset_tls_v6\n" - "+#else\n" - "+#define tls_emu\t\t0\n" - "+#define has_tls_reg\t\t0\n" - "+#define set_tls\t\tset_tls_software\n" - "+#endif\n" - "+\n" - "+#endif\t/* __ASMARM_TLS_H */\n" - "diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S\n" - "index 7ee48e7..a6cfb17 100644\n" - "--- a/arch/arm/kernel/entry-armv.S\n" - "+++ b/arch/arm/kernel/entry-armv.S\n" - "@@ -22,6 +22,7 @@\n" - " #include <asm/thread_notify.h>\n" - " #include <asm/unwind.h>\n" - " #include <asm/unistd.h>\n" - "+#include <asm/tls.h>\n" - " \n" - " #include \"entry-header.S\"\n" - " \n" - "@@ -739,12 +740,7 @@ ENTRY(__switch_to)\n" - " #ifdef CONFIG_MMU\n" - " \tldr\tr6, [r2, #TI_CPU_DOMAIN]\n" - " #endif\n" - "-#if defined(CONFIG_HAS_TLS_REG)\n" - "-\tmcr\tp15, 0, r3, c13, c0, 3\t\t@ set TLS register\n" - "-#elif !defined(CONFIG_TLS_REG_EMUL)\n" - "-\tmov\tr4, #0xffff0fff\n" - "-\tstr\tr3, [r4, #-15]\t\t\t@ TLS val at 0xffff0ff0\n" - "-#endif\n" - "+\tset_tls\tr3, r4, r5\n" - " #ifdef CONFIG_MMU\n" - " \tmcr\tp15, 0, r6, c3, c0, 0\t\t@ Set domain register\n" - " #endif\n" - "@@ -1009,17 +1005,12 @@ kuser_cmpxchg_fixup:\n" - " */\n" - " \n" - " __kuser_get_tls:\t\t\t\t@ 0xffff0fe0\n" - "-\n" - "-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)\n" - "-\tldr\tr0, [pc, #(16 - 8)]\t\t@ TLS stored at 0xffff0ff0\n" - "-#else\n" - "-\tmrc\tp15, 0, r0, c13, c0, 3\t\t@ read TLS register\n" - "-#endif\n" - "+\tldr\tr0, [pc, #(16 - 8)]\t@ read TLS, set in kuser_get_tls_init\n" - " \tusr_ret\tlr\n" - "-\n" - "-\t.rep\t5\n" - "-\t.word\t0\t\t\t@ pad up to __kuser_helper_version\n" - "-\t.endr\n" - "+\tmrc\tp15, 0, r0, c13, c0, 3\t@ 0xffff0fe8 hardware TLS code\n" - "+\t.rep\t4\n" - "+\t.word\t0\t\t\t@ 0xffff0ff0 software TLS value, then\n" - "+\t.endr\t\t\t\t@ pad up to __kuser_helper_version\n" - " \n" - " /*\n" - " * Reference declaration:\n" - "diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c\n" - "index 122d999..73921f1 100644\n" - "--- a/arch/arm/kernel/setup.c\n" - "+++ b/arch/arm/kernel/setup.c\n" - "@@ -269,6 +269,21 @@ static void __init cacheid_init(void)\n" - " extern struct proc_info_list *lookup_processor_type(unsigned int);\n" - " extern struct machine_desc *lookup_machine_type(unsigned int);\n" - " \n" - "+static void __init feat_v6_fixup(void)\n" - "+{\n" - "+\tint id = read_cpuid_id();\n" - "+\n" - "+\tif ((id & 0xff0f0000) != 0x41070000)\n" - "+\t\treturn;\n" - "+\n" - "+\t/*\n" - "+\t * HWCAP_TLS is available only on 1136 r1p0 and later,\n" - "+\t * see also kuser_get_tls_init.\n" - "+\t */\n" - "+\tif ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))\n" - "+\t\telf_hwcap &= ~HWCAP_TLS;\n" - "+}\n" - "+\n" - " static void __init setup_processor(void)\n" - " {\n" - " \tstruct proc_info_list *list;\n" - "@@ -311,6 +326,8 @@ static void __init setup_processor(void)\n" - " \telf_hwcap &= ~HWCAP_THUMB;\n" - " #endif\n" - " \n" - "+\tfeat_v6_fixup();\n" - "+\n" - " \tcacheid_init();\n" - " \tcpu_proc_init();\n" - " }\n" - "diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c\n" - "index 1621e53..cda78d5 100644\n" - "--- a/arch/arm/kernel/traps.c\n" - "+++ b/arch/arm/kernel/traps.c\n" - "@@ -30,6 +30,7 @@\n" - " #include <asm/unistd.h>\n" - " #include <asm/traps.h>\n" - " #include <asm/unwind.h>\n" - "+#include <asm/tls.h>\n" - " \n" - " #include \"ptrace.h\"\n" - " #include \"signal.h\"\n" - "@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)\n" - " \n" - " \tcase NR(set_tls):\n" - " \t\tthread->tp_value = regs->ARM_r0;\n" - "-#if defined(CONFIG_HAS_TLS_REG)\n" - "-\t\tasm (\"mcr p15, 0, %0, c13, c0, 3\" : : \"r\" (regs->ARM_r0) );\n" - "-#elif !defined(CONFIG_TLS_REG_EMUL)\n" - "-\t\t/*\n" - "-\t\t * User space must never try to access this directly.\n" - "-\t\t * Expect your app to break eventually if you do so.\n" - "-\t\t * The user helper at 0xffff0fe0 must be used instead.\n" - "-\t\t * (see entry-armv.S for details)\n" - "-\t\t */\n" - "-\t\t*((unsigned int *)0xffff0ff0) = regs->ARM_r0;\n" - "-#endif\n" - "+\t\tif (tls_emu)\n" - "+\t\t\treturn 0;\n" - "+\t\tif (has_tls_reg) {\n" - "+\t\t\tasm (\"mcr p15, 0, %0, c13, c0, 3\"\n" - "+\t\t\t\t: : \"r\" (regs->ARM_r0));\n" - "+\t\t} else {\n" - "+\t\t\t/*\n" - "+\t\t\t * User space must never try to access this directly.\n" - "+\t\t\t * Expect your app to break eventually if you do so.\n" - "+\t\t\t * The user helper at 0xffff0fe0 must be used instead.\n" - "+\t\t\t * (see entry-armv.S for details)\n" - "+\t\t\t */\n" - "+\t\t\t*((unsigned int *)0xffff0ff0) = regs->ARM_r0;\n" - "+\t\t}\n" - " \t\treturn 0;\n" - " \n" - " #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG\n" - "@@ -743,6 +747,16 @@ void __init trap_init(void)\n" - " \treturn;\n" - " }\n" - " \n" - "+static void __init kuser_get_tls_init(unsigned long vectors)\n" - "+{\n" - "+\t/*\n" - "+\t * vectors + 0xfe0 = __kuser_get_tls\n" - "+\t * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8\n" - "+\t */\n" - "+\tif (tls_emu || has_tls_reg)\n" - "+\t\tmemcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);\n" - "+}\n" - "+\n" - " void __init early_trap_init(void)\n" - " {\n" - " \tunsigned long vectors = CONFIG_VECTORS_BASE;\n" - "@@ -761,6 +775,11 @@ void __init early_trap_init(void)\n" - " \tmemcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);\n" - " \n" - " \t/*\n" - "+\t * Do processor specific fixups for the kuser helpers\n" - "+\t */\n" - "+\tkuser_get_tls_init(vectors);\n" - "+\n" - "+\t/*\n" - " \t * Copy signal return handlers into the vector page, and\n" - " \t * set sigreturn to be a pointer to these.\n" - " \t */\n" - "diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig\n" - "index 346ae14..71d5d5e 100644\n" - "--- a/arch/arm/mm/Kconfig\n" - "+++ b/arch/arm/mm/Kconfig\n" - "@@ -717,17 +717,6 @@ config TLS_REG_EMUL\n" - " \t a few prototypes like that in existence) and therefore access to\n" - " \t that required register must be emulated.\n" - " \n" - "-config HAS_TLS_REG\n" - "-\tbool\n" - "-\tdepends on !TLS_REG_EMUL\n" - "-\tdefault y if SMP || CPU_32v7\n" - "-\thelp\n" - "-\t This selects support for the CP15 thread register.\n" - "-\t It is defined to be available on some ARMv6 processors (including\n" - "-\t all SMP capable ARMv6's) or later processors. User space may\n" - "-\t assume directly accessing that register and always obtain the\n" - "-\t expected value only on ARMv7 and above.\n" - "-\n" - " config NEEDS_SYSCALL_FOR_CMPXCHG\n" - " \tbool\n" - " \thelp\n" - "diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S\n" - "index 7a5337e..2f5a3c2 100644\n" - "--- a/arch/arm/mm/proc-v6.S\n" - "+++ b/arch/arm/mm/proc-v6.S\n" - "@@ -239,7 +239,8 @@ __v6_proc_info:\n" - " \tb\t__v6_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA\n" - "+\t/* See also feat_v6_fixup() for HWCAP_TLS */\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS\n" - " \t.long\tcpu_v6_name\n" - " \t.long\tv6_processor_functions\n" - " \t.long\tv6wbi_tlb_fns\n" - "@@ -262,7 +263,7 @@ __pj4_v6_proc_info:\n" - " \tb\t__v6_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS\n" - " \t.long\tcpu_pj4_name\n" - " \t.long\tv6_processor_functions\n" - " \t.long\tv6wbi_tlb_fns\n" - "diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S\n" - "index 7aaf88a..8071bcd 100644\n" - "--- a/arch/arm/mm/proc-v7.S\n" - "+++ b/arch/arm/mm/proc-v7.S\n" - "@@ -344,7 +344,7 @@ __v7_proc_info:\n" - " \tb\t__v7_setup\n" - " \t.long\tcpu_arch_name\n" - " \t.long\tcpu_elf_name\n" - "-\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP\n" - "+\t.long\tHWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS\n" - " \t.long\tcpu_v7_name\n" - " \t.long\tv7_processor_functions\n" - " \t.long\tv7wbi_tlb_fns" + "Tony\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: arm-tls-v7.patch\n" + "Type: text/x-diff\n" + "Size: 8749 bytes\n" + "Desc: not available\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20100702/39043301/attachment.bin> -0344b2da6bc67a638a15ad7c359a624f9ea368260f9939a387e95bbe57cd5193 +01db183b0d27ece3fed16a1a0198951e4536437eb8313deb6b0e98acbb0d05c1
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