Re: [PATCH -v3] perf, x86: try to handle unknown nmis with running perfctrs

[Robert Richter <robert.richter@amd.com>]

On 27.08.10 11:05:23, Don Zickus wrote:
> The status masks seem to be identical, 0x1 (and when I forced pmc0
> unusable, everything was 0x2).

So this should also happen if only one counter is running?
Back-to-back nmis actually only occur then 2 different counters
trigger simultaneously.

> > > Now I wonder how the event was
> > > ever reloaded, unless it was by accident because of how the scheduler
> > > deals with perf counters (perf_start/stop all the time).
> > 
> > The nmi might be queued be the cpu regardless of of the overflow
> > state.
> > 
> > I am wondering why this happens at all, because events are disabled by
> > wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0). Hmm, maybe this is exactly the
> 
> Heh.  Not sure why it isn't working then.  Then again you shouldn't need
> the loop if it was working I would think.
> 
> > reason because the nmi could fire again after reenabling the counters.
> > 
> > Is there a reason for disabling all counters?
> 
> It would be a nice to have that way we wouldn't have to 'eat' all these
> extra nmis.  But I guess it isn't working correctly.

What about the erratum mentioned in this thread before? We might
identify affected cpus and return handled=2 for them. This solution
will be still better than before. And, all other cpu models have the
nmi detection fixed. In a next step we could try to use a timer for
detection.

-Robert

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Advanced Micro Devices, Inc.
Operating System Research Center