There is an errata in some of Intel processors.

AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6 During
an Interrupt Service Routine

If core C6 is entered after the start of an interrupt service routine but before
a write to the APIC EOI register, the core may not send an EOI transaction (if
needed) and further interrupts from the same priority level or lower may be
blocked.

This patch fix this issue, by checking if ISR is pending before enter deep Cx 
state. If so, it would use power->safe_state instead of deep Cx state to prevent 
the above issue happen.