Re: [PATCH 4/9] msix: move definitions from msix.c to msix.h

["Michael S. Tsirkin" <mst@redhat.com>]

On Mon, Sep 20, 2010 at 05:06:45PM +0200, Avi Kivity wrote:
> This allows us to reuse them from the kvm support code.
> 
> Signed-off-by: Avi Kivity <avi@redhat.com>

I would rather all dealings with MSI-X table stayed in one place. All we
need is just the entry, so let's add APIs to retrieve MSIX address and
data:

uint64_t msix_get_address(dev, vector)
uint32_t msix_get_data(dev, vector)

and that will be enough for KVM.

> ---
>  hw/msix.c |   27 ---------------------------
>  hw/msix.h |   26 ++++++++++++++++++++++++++
>  2 files changed, 26 insertions(+), 27 deletions(-)
> 
> diff --git a/hw/msix.c b/hw/msix.c
> index d762870..dda1a24 100644
> --- a/hw/msix.c
> +++ b/hw/msix.c
> @@ -16,33 +16,6 @@
>  #include "pci.h"
>  #include "kvm.h"
>  
> -/* MSI-X capability structure */
> -#define MSIX_TABLE_OFFSET 4
> -#define MSIX_PBA_OFFSET 8
> -#define MSIX_CAP_LENGTH 12
> -
> -/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
> -#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
> -#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
> -#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
> -
> -/* MSI-X table format */
> -#define MSIX_MSG_ADDR 0
> -#define MSIX_MSG_UPPER_ADDR 4
> -#define MSIX_MSG_DATA 8
> -#define MSIX_VECTOR_CTRL 12
> -#define MSIX_ENTRY_SIZE 16
> -#define MSIX_VECTOR_MASK 0x1
> -
> -/* How much space does an MSIX table need. */
> -/* The spec requires giving the table structure
> - * a 4K aligned region all by itself. */
> -#define MSIX_PAGE_SIZE 0x1000
> -/* Reserve second half of the page for pending bits */
> -#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
> -#define MSIX_MAX_ENTRIES 32
> -
> -
>  /* Flag for interrupt controller to declare MSI-X support */
>  int msix_supported;
>  
> diff --git a/hw/msix.h b/hw/msix.h
> index 6b21ffb..5c84b3e 100644
> --- a/hw/msix.h
> +++ b/hw/msix.h
> @@ -4,6 +4,32 @@
>  #include "qemu-common.h"
>  #include "pci.h"
>  
> +/* MSI-X capability structure */
> +#define MSIX_TABLE_OFFSET 4
> +#define MSIX_PBA_OFFSET 8
> +#define MSIX_CAP_LENGTH 12
> +
> +/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
> +#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
> +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
> +#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
> +
> +/* MSI-X table format */
> +#define MSIX_MSG_ADDR 0
> +#define MSIX_MSG_UPPER_ADDR 4
> +#define MSIX_MSG_DATA 8
> +#define MSIX_VECTOR_CTRL 12
> +#define MSIX_ENTRY_SIZE 16
> +#define MSIX_VECTOR_MASK 0x1
> +
> +/* How much space does an MSIX table need. */
> +/* The spec requires giving the table structure
> + * a 4K aligned region all by itself. */
> +#define MSIX_PAGE_SIZE 0x1000
> +/* Reserve second half of the page for pending bits */
> +#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
> +#define MSIX_MAX_ENTRIES 32
> +
>  int msix_init(PCIDevice *pdev, unsigned short nentries,
>                unsigned bar_nr, unsigned bar_size);
>  
> -- 
> 1.7.2.3