From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH] CHROMIUM: i915: Initialize panel timing
 registers if VBIOS did not.
Date: Thu, 7 Oct 2010 16:06:04 -0700
Message-ID: <20101007160604.5f2b2f76@jbarnes-desktop>
References: <AANLkTikoPjDs-RNs+nvOJUO5UWHedGjRT1Ee7kuDyVdO@mail.gmail.com>
	<8u3s8d$jqd8sk@orsmga001.jf.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from cpoproxy1-pub.bluehost.com (cpoproxy1-pub.bluehost.com
	[69.89.21.11])
	by gabe.freedesktop.org (Postfix) with SMTP id B20179ECA9
	for <intel-gfx@lists.freedesktop.org>;
	Thu,  7 Oct 2010 16:04:13 -0700 (PDT)
In-Reply-To: <8u3s8d$jqd8sk@orsmga001.jf.intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, Mandeep Baines <msb@chromium.org>, Olof Johansson <olofj@chromium.org>
List-Id: intel-gfx@lists.freedesktop.org

On Thu, 07 Oct 2010 23:55:38 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Thu, 7 Oct 2010 15:48:14 -0700, Bryan Freed <bfreed@chromium.org> wrote:
> > The time between start of the pixel clock and backlight enable is a basic
> > panel timing constraint.  If no VBIOS Table is found, and the Panel Power
> > On/Off registers are found to be 0, assume we are booting without VBIOS
> > initialization and set these registers to something reasonable.
> 
> IIRC, the panel sequence registers are meant to be stored in the VBIOS. So
> if we add the parsing of those to the driver and add the defaults to
> init_vbt_default() then we can check whether PP_ON_DELAYS is valid upon
> device init (module load and resume) and fixup in case the BIOS does not.

Right, those values should be in the VBT.  Getting them wrong can
actually damage your panel, so we need to take care here.  The whole
point of the power sequencing logic and register lock is to avoid such
damage.

That said, I've abused my panels (both LVDS and eDP) pretty hard and
have yet to damage one in any visible way, so stealing some
conservative (i.e. long) delays from an existing VBT will probably work
ok.

-- 
Jesse Barnes, Intel Open Source Technology Center