From: Andi Kleen <andi@firstfloor.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <andi@firstfloor.org>,
Eric Dumazet <eric.dumazet@gmail.com>,
Shaohua Li <shaohua.li@intel.com>,
lkml <linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@elte.hu>,
"hpa@zytor.com" <hpa@zytor.com>,
"Chen, Tim C" <tim.c.chen@intel.com>
Subject: Re: [PATCH 2/2]x86: spread tlb flush vector between nodes
Date: Wed, 20 Oct 2010 14:18:48 +0200 [thread overview]
Message-ID: <20101020121847.GE20124@basil.fritz.box> (raw)
In-Reply-To: <1287576512.3488.13.camel@twins>
On Wed, Oct 20, 2010 at 02:08:32PM +0200, Peter Zijlstra wrote:
> On Wed, 2010-10-20 at 14:06 +0200, Andi Kleen wrote:
> > On Wed, Oct 20, 2010 at 01:20:52PM +0200, Peter Zijlstra wrote:
> > > On Wed, 2010-10-20 at 09:31 +0200, Andi Kleen wrote:
> > > > Really a lot of the per CPU scaling we have today should be per core
> > > > or per node to avoid explosion.
> > >
> > > Shouldn't that be per-cache instead of per-core?
> >
> > That's the same on modern x86:
>
> Last time I checked there's more than 1 directory in arch/
Not sure what your point is?
I believe non x86 server processors have similar cache
layouts as the one I described, occasionally with another
cache level, and should do well with a similar setup.
For non server it typically doesn't matter too much
because there are not enough cores.
-Andi
--
ak@linux.intel.com -- Speaking for myself only.
next prev parent reply other threads:[~2010-10-20 12:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-20 3:07 [PATCH 2/2]x86: spread tlb flush vector between nodes Shaohua Li
2010-10-20 5:16 ` Eric Dumazet
2010-10-20 7:31 ` Andi Kleen
2010-10-20 11:20 ` Peter Zijlstra
2010-10-20 12:06 ` Andi Kleen
2010-10-20 12:08 ` Peter Zijlstra
2010-10-20 12:18 ` Andi Kleen [this message]
2010-10-20 7:30 ` Andi Kleen
2010-10-20 8:44 ` Shaohua Li
2010-10-20 23:07 ` [tip:x86/mm] x86: Spread " tip-bot for Shaohua Li
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