From: Ralf Baechle <ralf@linux-mips.org>
To: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 8/9] MIPS: Honor L2 bypass bit
Date: Thu, 21 Oct 2010 13:58:09 +0100 [thread overview]
Message-ID: <20101021125809.GA15031@linux-mips.org> (raw)
In-Reply-To: <74b5d3ba9506b2e6d885546bd6dcdaec@localhost>
On Wed, Oct 20, 2010 at 08:05:42PM -0700, Kevin Cernekee wrote:
> On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
> that the L2 cache is disabled and therefore Linux should not attempt
> to use it.
I did a bit of research in the meantime. Turns out that some MIPS
customers are using their own L2 cache controller. That means a simple
check by the CPU PrID is not sufficient and we will need some sort of
platform-specific probe, sigh.
I've moved all the code your patch adds to a separate function and added
a comment so at least people working on platforms with different L2
conntrollers will have a small chance of figuring out what mine blew up
under their feet.
Ralf
next prev parent reply other threads:[~2010-10-21 12:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-21 3:05 [PATCH v2 8/9] MIPS: Honor L2 bypass bit Kevin Cernekee
2010-10-21 3:05 ` Kevin Cernekee
2010-10-21 12:58 ` Ralf Baechle [this message]
2010-10-21 16:25 ` Kevin Cernekee
2010-10-24 2:40 ` Maciej W. Rozycki
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