Re: [bisected] Clocksource tsc unstable git

[Borislav Petkov <bp@amd64.org>]

On Fri, Oct 29, 2010 at 07:54:38AM -0400, Markus Trippelsdorf wrote:
> On Fri, Oct 29, 2010 at 01:39:34PM +0200, Borislav Petkov wrote:
> > On Fri, Oct 29, 2010 at 07:34:33AM -0400, Markus Trippelsdorf wrote:
> > > > Markus, can you verify this on your system by compiling x86info from
> > > > git://git.choralone.org/git/x86info and doing
> > > > 
> > > > ./lsmsr Int
> > > 
> > > 
> > > x86info v1.28beta.  Dave Jones 2001-2010
> > > Feedback to <davej@redhat.com>.
> > > 
> > > Found 4 CPUs
> > > --------------------------------------------------------------------------
> > > CPU #1
> > > EFamily: 1 EModel: 0 Family: 15 Model: 4 Stepping: 2
> > > CPU Model: Quad-Core Opteron/Phenom II (RB-C2)
> > 
> > well, x86info doesn't help - there's a lsmsr tool which is being built
> > too but no need, I can infer the info from your revision: your CPU is
> > RB-C2 which does SMI initiated C1E.
> 
> Sorry. Here is the correct output:
> 
> IntPendingMessage    = 0x0000000008c200b0

Yep, bit 27 is set, SmiOnCmpHalt.

Thanks.

-- 
Regards/Gruss,
Boris.

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