From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46498 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PIyYx-0006oE-NR for qemu-devel@nongnu.org; Thu, 18 Nov 2010 02:05:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PIyYw-0004wx-Di for qemu-devel@nongnu.org; Thu, 18 Nov 2010 02:05:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:64737) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PIyYw-0004wr-5m for qemu-devel@nongnu.org; Thu, 18 Nov 2010 02:05:42 -0500 Date: Thu, 18 Nov 2010 09:05:30 +0200 From: "Michael S. Tsirkin" Message-ID: <20101118070530.GB15274@redhat.com> References: <48f736e1a86a0db8ad368a42103d4e366a2dbd22.1289969012.git.yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <48f736e1a86a0db8ad368a42103d4e366a2dbd22.1289969012.git.yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH 7/7] pci bridge: implement secondary bus reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: skandasa@cisco.com, Anthony Liguori , etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote: > Emulates secondary bus reset when secondary bus reset bit > is written from 0 to 1. > > Signed-off-by: Isaku Yamahata > Signed-off-by: Anthony Liguori > --- > hw/pci_bridge.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > index 58cc2e4..618a81e 100644 > --- a/hw/pci_bridge.c > +++ b/hw/pci_bridge.c > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) > void pci_bridge_write_config(PCIDevice *d, > uint32_t address, uint32_t val, int len) > { > + PCIBridge *s = container_of(d, PCIBridge, dev); > + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + uint16_t bridge_control_new; > + > pci_default_write_config(d, address, val, len); > > if (/* io base/limit */ > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > /* memory base/limit, prefetchable base/limit and > io base/limit upper 16 */ > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > - PCIBridge *s = container_of(d, PCIBridge, dev); > pci_bridge_update_mappings(&s->sec_bus); > } > + > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { > + /* 0 -> 1 */ > + pci_bus_reset(&s->sec_bus); > + } > } > > void pci_bridge_disable_base_limit(PCIDevice *dev) Presumably this bit will have to be made writeable? > -- > 1.7.1.1