From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers
Date: Tue, 28 Dec 2010 18:00:03 +0100 [thread overview]
Message-ID: <20101228170003.GC375@linux-mips.org> (raw)
In-Reply-To: <1292889290-12849-3-git-send-email-ddaney@caviumnetworks.com>
On Mon, Dec 20, 2010 at 03:54:50PM -0800, David Daney wrote:
> If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they
> are more efficient than an AND followed by an branch and then
> restoring the clobbered register.
Queued for 2.6.38. Thanks,
Ralf
prev parent reply other threads:[~2010-12-28 17:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-20 23:54 [PATCH 0/2] MIPS: Use Octeon BBIT instructions in TLB handlers David Daney
2010-12-20 23:54 ` [PATCH 1/2] MIPS: Declare uasm bbit0 and bbit1 functions David Daney
2010-12-28 16:59 ` Ralf Baechle
2010-12-20 23:54 ` [PATCH 2/2] MIPS: Use BBIT instructions in TLB handlers David Daney
2010-12-28 17:00 ` Ralf Baechle [this message]
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