From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=36723 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PbaHY-0003yp-Dy for qemu-devel@nongnu.org; Sat, 08 Jan 2011 10:00:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PbaHS-0002kH-Vd for qemu-devel@nongnu.org; Sat, 08 Jan 2011 10:00:40 -0500 Received: from hall.aurel32.net ([88.191.126.93]:35793) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PbaHS-0002jH-R2 for qemu-devel@nongnu.org; Sat, 08 Jan 2011 10:00:34 -0500 Date: Sat, 8 Jan 2011 16:00:24 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 0/7] target-arm: Translate based on TB flags, not CPUState Message-ID: <20110108150024.GA5057@hall.aurel32.net> References: <1294412794-25573-1-git-send-email-peter.maydell@linaro.org> <20110107160117.GA25630@hall.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Sender: Aurelien Jarno List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org On Fri, Jan 07, 2011 at 05:50:51PM +0000, Peter Maydell wrote: > On 7 January 2011 16:01, Aurelien Jarno wrote: > > My other concern is about the definition of the individual bits in the > > flags. I have seen that you have tried to summarize the usage in the > > patch 6, but the masks and shifts are still duplicated in different > > files, which may leads to mistakes if the flags definition are changed. > > > > Have you considered using #define as for example in the MIPS target? > > I'll put out a proper v2 patchset in a bit but to save a round, > are you happy with the following set of #defines? > (I'm going to drop the comment since the #defines give the > same info.) > > /* Bit usage in the TB flags field: */ > #define ARM_TBFLAG_THUMB_SHIFT 0 > #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) > #define ARM_TBFLAG_VECLEN_SHIFT 1 > #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) > #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 > #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) > #define ARM_TBFLAG_PRIV_SHIFT 6 > #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) > #define ARM_TBFLAG_VFPEN_SHIFT 7 > #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) > #define ARM_TBFLAG_CONDEXEC_SHIFT 8 > #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) I am find with the names, maybe you can align the values for easier readability, but that's details. > /* some convenience accessor macros */ > #define ARM_TBFLAG_THUMB(F) \ > (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) > #define ARM_TBFLAG_VECLEN(F) \ > (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) > #define ARM_TBFLAG_VECSTRIDE(F) \ > (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) > #define ARM_TBFLAG_PRIV(F) \ > (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) > #define ARM_TBFLAG_VFPEN(F) \ > (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) > #define ARM_TBFLAG_CONDEXEC(F) \ > (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) > Looks fine. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net