Re: Regd: SPI Slave Select

[Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>]

Hi Tom,

On Fri, Jan 28, 2011 at 01:28:54PM +0530, Tom wrote:
> I have a SPI slave device which expects the slave select line to be active
> (low) during the entire message (e.g: say for a two byte transfer, the SS
> should be low for until both the bytes have been written, and should not go
> inactive in-between bytes being transfered).
> But, I notice, this is not the case. The SS goes inactive in between bytes
> transfer.
> 
> Does the spi framework provide any support to avoid SS being deactivated
> between byte transfer ?

This is a (mis)feature of the DesignWare SPI master hardware, when SCPOL = 1.  
See figure 16 (page 63) in the DesigWare DW_apb_ssi Databook. The only 
solution is to use an external GPIO to control the SS signal.

Another misfeature of this SPI master hardware is that it deactivates the SS 
signal automatically when the FIFO empties. This may or may not affect you, it 
depends on your application. Anyway, the solution here is again to use an 
external GPIO for SS.

baruch

> I have multiple slave devices on the same bus, so I can't keep the slave
> always selected.
> 
> My master driver is dw_spi.c and linunx kernel version is 2.6.35.
> 
> Regards,
> Tom

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