All of lore.kernel.org
 help / color / mirror / Atom feed
From: Tim Blechmann <tim@klingt.org>
To: Helmut Schaa <helmut.schaa@googlemail.com>
Cc: linux-wireless@vger.kernel.org
Subject: Re: rt61pci issue
Date: Thu, 17 Feb 2011 11:07:06 +0100	[thread overview]
Message-ID: <201102171107.07299.tim@klingt.org> (raw)
In-Reply-To: <201011282014.12465.helmut.schaa@googlemail.com>

> > > > > >> Mind to put a (maybe rate limited) printk into the interrupt
> > > > > >> thread that prints out "reg"
> > > > > >> and "reg_mcu" so that we can see which interrupts get triggered?
> > > > > > 
> > > > > > log attached, generated with:
> > > > > Thanks. Unfortunately nothing special in there. Mostly RX and TX
> > > > > interrupts. So there must be something else ...
> > > > 
> > > > Tim, is this on x86 hw? Or something else?
> > > 
> > > I don't know if this will do any good or harm but it could be worth a
> > > try as the spec for rt61pci says something like: "Don't enable
> > > interrupt mitigation in the same write as releasing the other masks.".
> > > Since we always write a mitigation period of 0xff == "No mitigation
> > > period" we can simply leave interrupt mitigation disabled.
> > > 
> > > I really don't have any clue if this will fix anything but it might be
> > > worth a try.
> > 
> > i have been running this patch for a few days and i haven't experienced
> > the problem again.
> 
> Ok, I'll officially submit the patch soon ...

i've been running a simple patch like for some time:
@ -1743,8 +1743,8 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
    rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
    rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
    rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
-   rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
-   rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
+   /* rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask); */
+   /* rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); */
    rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 
    rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
 
trying out the unpatched 2.6.38-rc5, i hit the original issue again. but with
the patch, i sometimes have connection troubles using skype. i would really
appreciate a proper solution for this issue ...

thanks, tim

-- 
tim@klingt.org
http://tim.klingt.org

You can play a shoestring if you're sincere
  John Coltrane

  reply	other threads:[~2011-02-17 11:53 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-11 13:02 rt61pci issue Tim Blechmann
2010-11-11 13:45 ` Helmut Schaa
     [not found]   ` <201011111556.31601.tim@klingt.org>
2010-11-11 15:13     ` Helmut Schaa
2010-11-12  6:47       ` Helmut Schaa
2010-11-12  7:03         ` Helmut Schaa
2010-11-25 17:19           ` Tim Blechmann
2010-11-28 19:14             ` Helmut Schaa
2011-02-17 10:07               ` Tim Blechmann [this message]
2010-11-12 13:49 ` Helmut Schaa
2010-11-12 16:03   ` Tim Blechmann

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=201102171107.07299.tim@klingt.org \
    --to=tim@klingt.org \
    --cc=helmut.schaa@googlemail.com \
    --cc=linux-wireless@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.