From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=35512 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q90E0-0003f6-CT for qemu-devel@nongnu.org; Sun, 10 Apr 2011 15:23:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q90Dz-00028h-9z for qemu-devel@nongnu.org; Sun, 10 Apr 2011 15:23:08 -0400 Received: from hall.aurel32.net ([88.191.126.93]:37277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q90Dz-00028a-1z for qemu-devel@nongnu.org; Sun, 10 Apr 2011 15:23:07 -0400 Date: Sun, 10 Apr 2011 21:23:02 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 15/15] tcg: use ext op for deposit Message-ID: <20110410192302.GB4551@volta.aurel32.net> References: <1301927544-32767-1-git-send-email-agraf@suse.de> <1301927544-32767-16-git-send-email-agraf@suse.de> <20110405045444.GH28617@hall.aurel32.net> <8E544975-03DA-484A-9768-41E2D1643074@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <8E544975-03DA-484A-9768-41E2D1643074@suse.de> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: peter.maydell@linaro.org, QEMU-devel Developers , Richard Henderson On Tue, Apr 05, 2011 at 09:55:09AM +0200, Alexander Graf wrote: > > On 05.04.2011, at 06:54, Aurelien Jarno wrote: > > > On Mon, Apr 04, 2011 at 04:32:24PM +0200, Alexander Graf wrote: > >> With the s390x target we use the deposit instruction to store 32bit values > >> into 64bit registers without clobbering the upper 32 bits. > >> > >> This specific operation can be optimized slightly by using the ext operation > >> instead of an explicit and in the deposit instruction. This patch adds that > >> special case to the generic deposit implementation. > >> > >> Signed-off-by: Alexander Graf > >> --- > >> tcg/tcg-op.h | 6 +++++- > >> 1 files changed, 5 insertions(+), 1 deletions(-) > > > > Have you really measuring a difference here? This should already be > > handled, at least on x86, by this code: > > > > if (TCG_TARGET_REG_BITS == 64) { > > if (val == 0xffffffffu) { > > tcg_out_ext32u(s, r0, r0); > > return; > > } > > if (val == (uint32_t)val) { > > /* AND with no high bits set can use a 32-bit operation. */ > > rexw = 0; > > } > > } > > I've certainly looked at the -d op logs and seen that instead of creating a const tcg variable plus an AND there was now an extu opcode issued, yes. No idea why the case up there didn't trigger. > The question there is looking at -d out_asm. They should be the same at the end as the code I pasted above is from tcg/i386/tcg-target.c. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net